参数资料
型号: MAX1777EEI+T
厂商: Maxim Integrated
文件页数: 26/32页
文件大小: 0K
描述: IC REG QD BUCK/LINEAR 28QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: 降压(降压)(2),线性(LDO)(2)
功能: 任何功能
输出数: 4
频率 - 开关: 200kHz ~ 500kHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 控制器
电压/电流 - 输出 3: 3.3V,100mA
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 4.5 V ~ 24 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.154",3.90mm 宽)
供应商设备封装: 28-QSOP
包装: 带卷 (TR)
High-Efficiency, Quad Output, Main Power-
Supply Controllers for Notebook Computers
When using low-capacity filter capacitors such as
polymer types, capacitor size is usually determined by
the capacity required to prevent V SAG and V SOAR from
tripping the undervoltage and overvoltage fault latches
during load transients in ultrasonic mode .
For low input-to-output voltage differentials (V IN /V OUT <2),
additional output capacitance is required to maintain sta-
bility and good efficiency in ultrasonic mode.
The amount of overshoot due to stored inductor energy
can be calculated as:
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feed-
back loop instability. Noise on the output or insufficient
ESR may cause double pulsing. Insufficient ESR does
not allow the amplitude of the voltage ramp in the output
signal to be large enough. The error comparator mistak-
enly triggers a new cycle immediately after the 350ns
minimum off-time period has expired. Double pulsing
results in increased output ripple, and can indicate the
presence of loop instability caused by insufficient ESR.
Loop instability results in oscillations or ringing at the
V SOAR =
L × I PEAK 2
2 × C × V OUT _
output after line or load perturbations, causing the out-
put voltage to fall below the tolerance limit.
The easiest method for checking stability is to apply a
where I PEAK is the peak inductor current.
Stability Considerations
Stability is determined by the value of the ESR zero
(f ESR ) relative to the switching frequency (f). The point
of instability is given by the following equation:
very fast zero-to-max load transient (refer to the
MAX1999 EV kit data sheet) and observe the output
voltage-ripple envelope for overshoot and ringing.
Monitoring the inductor current with an AC current
probe may also provide some insight. Do not allow
more than one cycle of ringing of under- or overshoot
where:
f ESR ≤
f
π
after the initial step response.
Input Capacitor Selection
The input capacitors must meet the input ripple current
(I RMS ) requirement imposed by the switching current.
f ESR =
1
2 × π × R ESR × C OUT
The MAX1777/MAX1977/MAX1999 dual switching regu-
lators operate at different frequencies. This interleaves
the current pulses drawn by the two switches and
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Low-ESR capacitors (especially polymer or tantalum),
in widespread use at the time of publication, typically
have ESR zero frequencies lower than of 30kHz. In the
design example used for inductor selection, the ESR
reduces the overlap time where they add together. The
input RMS current is much smaller in comparison than
with both SMPSs operating in phase. The input RMS cur-
rent varies with load and the input voltage.
The maximum input capacitor RMS current for a single
SMPS is given by:
ESR =
(
? V OUT _ V + ? V OUT _
I RMS ≈ I LOAD ?
) ? ?
needed to support a specified ripple voltage is found
by the equation:
V RIPPLE ( P ? P )
LIR × I LOAD
?
?
? V +
?
?
?
where LIR is the inductor ripple current ratio and I LOAD
is the average DC load. Using a LIR = 0.35 and an
average load current of 5A, the ESR needed to support
50mV P-P ripple is 28m ? .
Do not place high-value ceramic capacitors directly
across the fast-feedback inputs (OUT_ to GND for inter-
nal feedback, FB_ divider point for external feedback)
without taking precautions to ensure stability. Large
ceramic capacitors can have a high-ESR zero frequency
and cause erratic, unstable operation. Adding a discrete
resistor or placing the capacitors a couple of inches
downstream from the junction of the inductor and OUT_
may improve stability.
when V+ = 2 x V OUT_ (D = 50%), I RMS has maximum
current of I LOAD /2.
The ESR of the input capacitor is important for deter-
mining capacitor power dissipation. All the power
(I 2RMS x ESR) heats up the capacitor and reduces effi-
ciency. Nontantalum chemistries (ceramic or OS-CON)
are preferred due to their low ESR and resilience to
power-up surge currents. Choose input capacitors that
exhibit less than +10°C temperature rise at the RMS
input current for optimal circuit longevity. Place the
drains of the high-side switches close to each other to
share common input bypass capacitors.
26
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