参数资料
型号: MAX1845ETX
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 稳压器
英文描述: Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
中文描述: DUAL SWITCHING CONTROLLER, 620 kHz SWITCHING FREQ-MAX, QCC36
封装: 6 X 6 MM, 0.80 MM, MO220WJJD-1, TQFN-36
文件页数: 16/27页
文件大小: 543K
代理商: MAX1845ETX
M
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
16
______________________________________________________________________________________
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
circuit to work properly. Otherwise, the sense circuitry
in the MAX1845 will interpret the MOSFET gate as
off
while there is actually still charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50
to 100 mils wide if the MOSFET is 1 inch from the
MAX1845).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.5
typical on-resistance. This helps
prevent DL from being pulled up during the fast rise-
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronous-
rectifier MOSFET. However, for high-current applica-
tions, some combinations of high- and low-side FETs
might be encountered that will cause excessive gate-
drain coupling, which can lead to efficiency-killing,
EMI-producing shoot-through currents. This is often
remedied by adding a resistor in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 6).
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V
CC
rises above
approximately 2V, resetting the fault latch and soft-start
counter and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switch-
ing. DL is low if the overvoltage protection (OVP) is dis-
abled. DL is high if the overvoltage protection is
enabled (see the
Output Overvoltage Protection
sec-
tion) when V
CC
rises above 4.2V, whereupon an inter-
nal digital soft-start timer begins to ramp up the
maximum allowed current limit. The ramp occurs in five
steps: 20%, 40%, 60%, 80%, and 100%; 100% current
is available after 1.7ms ±50%.
A continuously adjustable analog soft-start function can
be realized by adding a capacitor in parallel with the
ILIM external resistor-divider network. This soft-start
method requires a minimum interval between power-
down and power-up to discharge the capacitor.
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors
the output voltage for both overvoltage and undervolt-
age conditions. In shutdown, standby, and soft-start,
PGOOD is actively held low. After a digital soft-start
has terminated, PGOOD is released when the output is
within 10% of the error-comparator threshold. The
PGOOD output is a true open-drain type with no para-
sitic ESD diodes. Note that the PGOOD window detec-
tor is independent of the output overvoltage and
undervoltage protection (UVP) thresholds.
Output Overvoltage Protection
The output voltage can be continuously monitored for
overvoltage. When overvoltage protection is enabled, if
the output exceeds the overvoltage threshold, overvolt-
age protection is triggered and the DL low-side gate-
drivers are forced high. This activates the low-side
MOSFET switch, which rapidly discharges the output
capacitor and reduces the input voltage.
Note that DL latching high causes the output voltage to
dip slightly negative when energy has been previously
stored in the LC tank circuit. For loads that cannot toler-
ate a negative voltage, place a power Schottky diode
across the output to act as a reverse polarity clamp.
Connect OVP to GND to enable the default trip level of
114% of the nominal output. To adjust the overvoltage
protection trip level, apply a voltage from 1V (100%) to
1.8V (180%) at OVP. Disable the overvoltage protection
by connecting OVP to V
CC
.
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
I
I
LOAD
= I
PEAK
/2
ON-TIME
0
TIME
I
PEAK
L
V
BATT
-V
OUT
i
t
=
Figure 5.
‘‘
Valley
’’
Current-Limit Threshold Point
I
I
LIMIT
I
LOAD
0
TIME
I
PEAK
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