参数资料
型号: MAX186ACWP
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: ADC
英文描述: Low-Power, 8-Channel, Serial 12-Bit ADCs
中文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封装: SO-20
文件页数: 5/24页
文件大小: 245K
代理商: MAX186ACWP
Note 1:
Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4:
Ground on-channel; sine wave applied to all off channels.
Note 5:
Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
Measured at V
SUPPLY
+5% and V
SUPPLY
-5% only.
Note 9:
The common-mode range for the analog inputs is from V
SS
to V
DD
.
M
Low-Power, 8-Channel,
S erial 12-Bit ADCs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
UNITS
Positive Supply Rejection
(Note 8)
Negative Supply Rejection
(Note 8)
PSR
±0.06
±0.5
mV
PSR
V
SS
= -5V ±5%; external reference, 4.096V;
full-scale input
±0.01
±0.5
mV
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7μF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; V
SS
=0V or -5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
UNITS
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
Fall to SSTRB Output Enable
(Note 6)
CS
Rise to SSTRB Output Disable
(Note 6)
t
CL
200
ns
ns
t
SSTRB
C
LOAD
= 100pF
200
t
SDV
External clock mode only, C
LOAD
= 100pF
200
ns
t
STR
External clock mode only, C
LOAD
= 100pF
200
ns
t
SCK
Internal clock mode only
0
ns
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
t
AZ
t
DS
t
DH
1.5
100
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
C
LOAD
= 100pF
20
20
150
200
100
100
SCLK Fall to Output Data Valid
t
DO
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
t
DV
t
TR
t
CSS
t
CSH
t
CH
C
LOAD
= 100pF
C
LOAD
= 100pF
100
0
200
MAX18_ _C/E
MAX18_ _M
SSTRB Rise to SCLK Rise
(Note 6)
V
DD
= 5V ±5%; external reference, 4.096V;
full-scale input
MIN
TYP
MAX
MIN
TYP
MAX
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