参数资料
型号: MAX1876EEG+T
厂商: Maxim Integrated Products
文件页数: 17/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 660kHz
占空比: 90%
电源电压: 4.75 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
N L _ according to duty factor as shown in the equations
50
BODE PLOT FOR VOLTAGE-
MODE CONTROLLERS
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
40
30
f LC
Calculate MOSFET temperature rise according to pack-
age thermal-resistance specifications to ensure that
20
10
f Z-COMP_A
f ESR
f CO
f SWITCH
both MOSFETs are within their maximum junction tem-
perature at high ambient temperature. The worst-case
dissipation for the high-side MOSFET (P NH ) occurs at
0
-10
both extremes of input voltage, and the worst-case dis-
sipation for the low-side MOSFET (P NL ) occurs at maxi-
-20
f COMP_B
mum input voltage.
P NH ( SWITCHING ) = IN LOAD OSC ? GS GD ?
-30
-40
0.001
0.01
0.1
1
V I f ? Q + Q ?
2 ? I GATE ?
FREQUENCY (MHz)
Figure 8. Voltage-Mode Loop Analysis
I GATE is the average DH driver output current capability
determined by:
? Minimum threshold voltage (V TH(MIN) )
? Total gate charge (Q g )
I GATE =
2 ( R DS ( ON ) DH + R GATE
V L
)
P NH ( CONDUCTION ) = I LOAD DS ( ON ) NH ? OUT ?
P NL = I LOAD R DS ( ON ) NL ? 1- ? OUT ? ?
? Reverse transfer capacitance (C RSS )
? Power dissipation
All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V GS ≥
4.5V. For maximum efficiency, choose a high-side
MOSFET (N H _) that has conduction losses equal to the
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
Ensure that the MAX1875/MAX1876 DL_ gate drivers
can drive N L _. In particular, check that the dv/dt
caused by N H _ turning on does not pull up the N L _
gate through N L _ ’ s drain-to-gate capacitance. This is
the most frequent cause of cross-conduction problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that V L can
power all four drivers without overheating the IC:
P VL = V IN × Q G _ TOTAL × f SW
MOSFET package power dissipation often becomes a
dominant design factor. I 2 R power losses are the great-
est heat contributor for both high-side and low-side
MOSFETs. I 2 R losses are distributed between N H _ and
where R DS(ON)DH is the high-side MOSFET driver ’ s on-
resistance (5 ? max), and R GATE is any series resis-
tance between DH and BST (Figure 3).
2 ? V ?
R
? V IN ?
P NH ( TOTAL ) = P NH ( SWITCHING ) + P NH ( CONDUCTION )
2 ? ? V ? ?
? ? V IN ? ?
where P NH(CONDUCTION) is the conduction power loss
in the high-side MOSFET, and P NL is the total low-side
power loss.
To reduce EMI caused by switching noise, add a 0.1μF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs ’ turn-on
and turn-off times.
Applications Information
Dropout Performance
When working with low input voltages, the output-volt-
age adjustable range for continuous-conduction opera-
tion is restricted by the minimum off-time (t OFF(MIN) ).
For best dropout performance, use the lowest (100kHz)
switching-frequency setting. Manufacturing tolerances
and internal propagation delays introduce an error to
______________________________________________________________________________________
17
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