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参数资料
| 型号： | MAX1876EEG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 660kHz |
| 占空比： | 90% |
| 电源电压： | 4.75 V ~ 23 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
? Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency by 1% or more.
? LX_ and PGND connections to the synchronous rec-
tifiers for current limiting must be made using Kelvin
sense connections to guarantee the current-limit
accuracy. With 8-pin SO MOSFETs, this is best done
by routing power to the MOSFETs from outside
using the top copper layer, while connecting PGND
and LX_ underneath the 8-pin SO package.
? When trade-offs in trace lengths must be made,
allow the inductor-charging path to be made longer
than the discharge path. Since the average input
current is lower than the average output current in
step-down converters, this minimizes the power dis-
sipation and voltage drops caused by board resis-
tance. For example, allow some extra distance
between the input capacitors and the high-side
MOSFET rather than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
? Ensure that the feedback connection to C OUT_ is
short and direct.
? Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas
(REF, COMP_, ILIM_, and FB_). Use PGND1 and
PGND2 as EMI shields to keep radiated noise away
from the IC, feedback dividers, and analog bypass
capacitors.
? Make all pin-strap control input connections (ILIM_,
SYNC, and EN) to analog ground (GND) rather than
power ground (PGND).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (N L _ source, C IN _, and C OUT _). Make
all these connections on the top layer with wide, cop-
per-filled areas (2oz copper recommended).
2) Mount the controller IC adjacent to the synchronous
rectifier MOSFETs (N L _), preferably on the back
side in order to keep LX_, PGND_, and DL_ traces
short and wide. The DL_ gate trace must be short
and wide, measuring 50mils to 100mils wide if the
low-side MOSFET is 1in from the controller IC.
3) Group the gate-drive components (BST_ diodes and
capacitors, and V L bypass capacitor) together near
the controller IC.
4) Make the DC-DC controller ground connections as
follows: create a small analog ground plane near the
IC. Connect this plane to GND and use this plane for
the ground connection for the reference (REF) V+
bypass capacitor, compensation components, feed-
back dividers, OSC resistor, and ILIM_ resistors (if
any). Connect GND and PGND together under the
IC (this is the only connection between GND and
PGND).
5) On the board ’ s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
Chip Information
TRANSISTOR COUNT: 6688
PROCESS: BiCMOS
______________________________________________________________________________________
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