参数资料
型号: MAX194AMDE
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: ADC
英文描述: 14-Bit, 85ksps ADC with 10A Shutdown
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16
封装: SIDEBRAZED, CERAMIC, DIP-16
文件页数: 7/24页
文件大小: 223K
代理商: MAX194AMDE
If the power supplies do not settle within the MAX194’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrat-
ed. If so, recalibrate the converter (pulse
RESET
low)
before use. For best DC accuracy, calibrate the
MAX194 any time there is a significant change in sup-
ply voltages, temperature, reference voltage, or clock
characteristics (see External Clock section) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parame-
ters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to main-
tain accuracy or to recalibrate if the MAX194 has been
held in shutdown for long periods. However, recalibra-
tion is recommended if it is likely that supply voltages or
ambient temperature has significantly changed since
the previous calibration.
Digital Interfac e
The digital interface pins consist of BP/UP/
SHDN
, CLK,
SCLK,
EOC
,
CS
,
CONV
, and
RESET
.
BP/UP/
SHDN
is a three-level input. Leave it floating to
configure the MAX194’s analog input in bipolar mode
(AIN = -V
REF
to V
REF
) or connect it high for a unipolar
input (AIN = 0V to V
REF
). Bringing BP/UP/
SHDN
low
places the MAX194 in its 10μA shutdown mode.
A logic low on
RESET
halts MAX194 operation. The ris-
ing edge of
RESET
initiates calibration as described in
the Calibrationsection above.
Begin a conversion by bringing
CONV
low. The convert
signal must be synchronized with CLK. The falling edge
of
CONV
must occur during the period shown in
Figures 3 and 4. When CLK is not directly controlled by
your processor, two methods of ensuring synchroniza-
tion are to drive
CONV
from
EOC
(continuous conver-
sions) or to gate the conversion-start signal with the
conversion clock so that
CONV
can go low only while
CLK is low (Figure 5). Ensure that the maximum propa-
gation delay through the gate is less than 40ns.
The MAX194 automatically ensures four CLK periods
for track/hold acquisition. If, when
CONV
is asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and
EOC
will go high on the
following falling CLK edge (Figure 3). After conversion
begins, additional convert start pulses are ignored. If,
when convert is asserted, less than three clock cycles
have passed, a conversion will begin on the fourth
falling clock edge after the end of the previous conver-
M
14-Bit, 85ksps ADC with 10μA S hutdown
_______________________________________________________________________________________
7
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
t
AQ
*
*
THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
t
CEL
t
CW
t
CEH
t
CC2
t
CC1
EOC
CONV
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
相关PDF资料
PDF描述
MAX194BEPE Fixed-Point Digital Signal Processor 532-FCBGA
MAX194BEWE 14-Bit, 85ksps ADC with 10A Shutdown
MAX194BMDE 14-Bit, 85ksps ADC with 10A Shutdown
MAX195ACDE 16-Bit, 85ksps ADC with 10レA Shutdown
MAX195AEDE 16-Bit, 85ksps ADC with 10レA Shutdown
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