参数资料
型号: MAX1962EEP+T
厂商: Maxim Integrated Products
文件页数: 16/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.12MHz
占空比: 90%
电源电压: 2.35 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
V IN
GAIN (dB)
DH
MAX1960
LX
DL
FB
L O
R3
R2
C 0
C3
V OUT
R4
R1
COMP
fp1
fz1
fz2
fp2
fp3
FREQUENCY
C2
Figure 5. Type 3 Compensation Network
where:
C1
Figure 6. Transfer Function for Type 3 Compensation
If C2 < 10pF, it can be omitted.
V IN(MAX) = Maximum input voltage
V RAMP = Oscillator ramp voltage = 0.85 x 10 6 /f S ,
where f S = switching frequency
C 3 ≤
2 π × f 0 × L 0 × C 0 × V RAMP
R 1 × V IN
L O = Output inductance
C O = Output capacitance
Place the second pole after the ESR zero:
The goal is to place the two zeros below crossover and
the two poles above crossover so that crossover
occurs with a single-pole slope. The compensation pro-
cedure is as follows:
Select the crossover frequency such that:
If:
R 2 ≤
1
2 π × f ZESR × C 3
f 0 < f ZESR and f 0 <1/5   f S
Select R1 such that:
R 2 <
1
g mEA
,
R 1 >>
2
g mEA
where g mEA = 2mS
increase R1 and recalculate C1, C2, and C3.
Place the second zero at the double-pole frequency:
where g mEA = 2mS.
Place the first zero before the double pole:
R 3 ≥
1
2 π × f LC × C 3
- R 2
C 1 ≥
1
2 π × 0 . 75 × f LC × R 1
Set the output voltage:
Place the third pole at half the switching frequency:
1
C 2 ≥
2 π × 0 . 5 × f S × R 1
R 4 =
V FB
V OUT - V FB
× R 3 , V FB = 0 . 8 V
16
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