参数资料
型号: MAX1962EEP+T
厂商: Maxim Integrated Products
文件页数: 17/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.12MHz
占空比: 90%
电源电压: 2.35 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
The feedback divider has a gain of G FB = V FB /V OUT ,
Compensation with Electrolytic Output Capacitors
The MAX1960/MAX1961/MAX1962 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
where V FB is 0.8V.
The transconductance error amplifier has DC gain
GEA(dc) of 80dB. A dominant pole is set by the com-
pensation capacitor (C C ), the amplifier output resis-
tance (R O ), and the compensation resistor (R C ):
The inductor and output capacitor create a double pole
at the resonant frequency, which has gain drop of 40dB
per decade, and phase shift of 180 ° . The error amplifier
must compensate for this gain drop and phase shift in
f PEA =
1
2 π × C C × ( R 0 + R C )
order to achieve a stable high-bandwidth, closed-loop
system.
The basic regulator loop consists of a power modulator,
A zero is set by the compensation resistor and the
compensation capacitor:
an output feedback divider and an error amplifier. The
power modulator has DC gain set by V IN /V RAMP , with a
double pole set by the inductor and output capacitor,
f ZEA =
1
2 π × C C × R C
G MOD ( DC ) =
f ZESR < f C ≤ S
and a single zero set by the output capacitor (C O ) and
its equivalent series resistance (ESR). Below are equa-
tions that define the power modulator:
The DC gain of the power modulator is:
V IN
V RAMP
where V RAMP = 0.85 × 10 6 / f S . The pole frequency due
to the inductor and output capacitor is:
The total closed-loop gain must equal to unity at the
crossover frequency, where the crossover frequency
should be higher than f ZESR , so that the -1 slope is
used to cross over at unity gain. Also, the crossover
frequency should be less than or equal to 1/5 the
switching frequency.
f
5
The loop-gain equation at the crossover frequency is:
f PMOD =
1
2 π L O C O
V FB
V OUT
× G EA ( f C ) × G MOD ( f C ) = 1
The zero frequency due to the output capacitor’s ESR
is:
where:
f ZESR =
1
2 π × R ESR × C O
and:
G EA ( f C ) = g mEA × R C
The output capacitor is usually comprised of several
same value capacitors connected in parallel. With n
capacitors in parallel, the output capacitance is:
G MOD ( f C ) = G MOD ( DC ) ×
(f PMOD )2
f ESR × f C
C O = n × C EACH
The compensation resistor, R C , is calculated from:
g mEA FB MOD ( f C )
The total ESR is:
R C =
V OUT
× V × G
R ESR =
R ESR(EACH)
n
where g mEA = 2mS.
Due to the under-damped (Q > 1) nature of the output
The ESR zero (f ZESR ) for a parallel combination of
capacitors is the same as for an individual capacitor.
LC double pole, the error-amplifier compensation zero
should be approximately 0.2f PMOD to provide good
phase boost. C C is calculated from:
______________________________________________________________________________________
17
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