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参数资料
| 型号： | MAX196BMYI |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | Multirange, Single %V, 12-Bit DAS with 12-Bit Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封装： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件页数： | 5/16页 |
| 文件大小： | 165K |
| 代理商： | MAX196BMYI |
M
Multirange, S ingle +5V, 12-Bit DAS
with 12-Bit Bus Interfac e
_______________________________________________________________________________________
5
Note 1:
Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Ground “on” channel; sine wave applied to all “off” channels.
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Guaranteed by design. Not tested.
Use static loads only.
Tested using internal reference.
PSRR measured at full-scale.
External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10:
Not subject to production testing. Provided for design guidance only.
Note 11:
All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
Note 12:
t
DO
is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13:
t
TR
is defined as the time required for the data lines to change by 0.5V.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are at T
A
= +25°C.)
Three-State Output Capacitance
C
OUT
15
pF
(Note 5)
Output High Voltage
V
OH
V
DD
- 1
V
V
DD
= 4.75V, I
SOURCE
= 1mA
Output Low Voltage
V
OL
0.4
V
V
DD
= 4.75V, I
SINK
= 1.6mA
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
DIGITAL OUTPUTS
(D11–D0, INT)
RD Low to Output Data Valid
RD High to Output Disable
t
DO
t
TR
120
70
ns
ns
Figure 2, C
L
= 100pF (Note 12)
(Note 13)
Data Valid to WR Setup
Data Valid to WR Hold
t
DH
0
ns
t
DS
60
ns
CLK to WR Setup Time
CLK to WR Hold Time
t
CWH
50
ns
t
CWS
100
ns
CS to RD Setup Time
CS to RD Hold Time
t
CSRH
0
ns
t
CSRS
0
ns
CS to WR Setup Time
CS to WR Hold Time
t
CSWH
0
ns
t
CSWS
0
ns
WR Pulse Width
t
WR
80
ns
PARAMETER
SYMBOL
t
CS
MIN
80
TYP
MAX
UNITS
ns
CS Pulse Width
RD Low to INT High Delay
t
INT1
120
ns
CONDITIONS
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