参数资料
型号: MAX1993ETG+
厂商: Maxim Integrated Products
文件页数: 33/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 75
系列: Quick-PWM™
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
Quick-PWM Step-Down Controllers with Inductor
Saturation Protection and Dynamic Output Voltages
V DDQ
V CC
V IN
SKIP
DH
C IN
V TT = DDQ
1000pF
10k Ω
LX
L
R SENSE
V
2
REFIN
DL
C OUT
1000pF
10k Ω
OD
MAX1993 GND
CSP
CSN
Figure 12. Active Bus Termination
GATE
FBLANK
OUT
FB
V DDQ = DDR MEMORY SUPPLY VOLTAGE
V TT = TERMINATION SUPPLY VOLTAGE
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 15). If possible, mount all of the power compo-
nents on the topside of the board, with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
? Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
? Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
? Minimize current-sensing errors by connecting CSP
and CSN directly across the current-sense resistor
(R SENSE ).
? When trade-offs in trace lengths must be made, it is
preferable to allow the inductor-charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
? Route high-speed switching nodes (BST, LX, DH,
and DL) away from sensitive analog areas (REF, FB,
CSP, and CSN).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (N L source, C IN , C OUT , and D L
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the backside opposite N L
and N H in order to keep LX, GND, DH, and the DL
gate-drive lines short and wide. The DL and DH gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper adap-
tive dead-time sensing.
3) Group the gate-drive components (BST diode and
capacitor, V DD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 9. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power compo-
nents go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single point
directly at the IC.
5) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-to-DC con-
verter circuit as close to the load as is practical.
______________________________________________________________________________________
33
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