参数资料
型号: MAX2036CCQ+
厂商: Maxim Integrated Products
文件页数: 22/25页
文件大小: 0K
描述: IC VGA W/OCTAL MIXER 8CH 100TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
放大器类型: 可变增益
电路数: 8
输出类型: 差分
-3db带宽: 2MHz
电流 - 电源: 245mA
电流 - 输出 / 通道: 3.75mA
电压 - 电源,单路/双路(±): 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 托盘
MAX2036
Ultrasound VGA Integrated
with CW Octal Mixer
6
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE (continued)
(Figure 7, VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0, CW_FILTER = 1, TEST_MODE =
0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz, capacitance to GND at each of the
VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1k, CW mixer outputs pulled up to
+11V through four separate ±0.1% 115
resistors, differential mixer inputs are driven from a low-impedance source. Typical values are
at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL SHIFT REGISTER
Serial Shift Register Programming
Rate
10
MHz
Minimum Data Set-Up Time
tDSU
30
ns
Minimum Data Hold Time
tHLD
2ns
Minimum Data Clock Time
tDCLK
100
ns
Minimum Data Clock Pulse Width
High
tDCLKPWH
30
ns
Minimum Data Clock Pulse Width
Low
tDCLKPWL
30
ns
Minimum Load Line
tLD
30
ns
Minimum Load Line High to Mixer
Clock On
tMIXCLK
30
ns
Minimum Data Clock to Load
Line High
tCLH
30
ns
Note 2: Specifications at TA = +25°C and TA = +70°C are guaranteed by production. Specifications at TA = 0°C are guaranteed by
design and characterization.
Note 3: Noise performance of the device is dependent on the noise contribution from the supply to VREF. Use a low-noise supply
for VREF. VCC and VREF can be connected together to share the same supply voltage if the supply for VCC exhibits low
noise.
Note 4: Total on-chip power dissipation is calculated as PDISS = VCC x ICC + VREF x IREF + [11V - (IMIX/4) x 115] x IMIX.
Note 5: Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes there to be a period of time (related to the RC time constant) when the DC level on the
chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not exceed both the
logic thresholds required for proper operation. This problem associated with AC-coupling would cause an inability to
ensure synchronization among beamforming channels. The LVDS signal is terminated differentially with an external 100
resistor on the board.
Note 6: External 100
resistor terminates the LVDS differential signal path.
Note 7: The mixer common-mode current (3.25mA/channel) is specified as the common-mode current in each of the differential
mixer outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+, CW_IOUT-).
Note 8: Specification guaranteed only for DOUT driving DIN of the next device in a daisy-chain fashion.
Note 9: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive and
a switching network is recommended as shown in the
Applications Information section.
Note 10: See the
Ultrasound-Specific IMD3 Specification in the Applications Information section.
Note 11: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 12: Channel-to-channel gain-and-phase matching measured on 30 pieces during engineering characterization at room temper-
ature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the angle
of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the phase
variation.
Note 13: Transconductance is defined as the quadrature summing of the CW differential output current at baseband divided by the
mixer’s input voltage.
相关PDF资料
PDF描述
MAX2470EUT+T IC AMP VCO BUFFER DIFF SOT23-6
MAX2472EUT+T IC VCO BUFFER AMP SOT23-6
MAX34406HETG+T IC AMP CURR SENSE QUAD 24TQFN
MAX3798ETJ+T IC LIMITING AMP/VCSEL DVR 32TQFN
MAX400CPA+ IC OPAMP ULTRA LOW OFFSET 8-DIP
相关代理商/技术参数
参数描述
MAX2036CCQ+ 功能描述:仪表放大器 Ultrasound Variable Gain Amplifier RoHS:否 制造商:Texas Instruments 通道数量: 输入补偿电压:150 V 可用增益调整: 最大输入电阻:10 kOhms 共模抑制比(最小值):88 dB 工作电源电压:2.7 V to 36 V 电源电流:200 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:MSOP-8 封装:Bulk
MAX2036CCQ+D 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
MAX2036CCQ+T 功能描述:仪表放大器 Ultrasound Variable Gain Amplifier RoHS:否 制造商:Texas Instruments 通道数量: 输入补偿电压:150 V 可用增益调整: 最大输入电阻:10 kOhms 共模抑制比(最小值):88 dB 工作电源电压:2.7 V to 36 V 电源电流:200 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:MSOP-8 封装:Bulk
MAX2036CCQ+TD 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Ultrasound VGA Integrated with CW Octal Mixer
MAX2036EVKIT 制造商:Maxim Integrated Products 功能描述:ULTRASOUND VARIABLE-GAIN AMPLIFIER WITH CWD (10B COMPATIBLE - Boxed Product (Development Kits)