参数资料
型号: MAX2062ETM+
厂商: Maxim Integrated
文件页数: 16/24页
文件大小: 0K
描述: IC VGA ANALOG/DIGITAL 48TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
频率: 50MHz ~ 1GHz
P1dB: 18.8dB
增益: 16.5dB
噪音数据: 9dB
RF 型: 通用
电源电压: 3.135 V ~ 3.465 V,4.75 V ~ 5.25 V
电流 - 电源: 148mA
测试频率: 900MHz
封装/外壳: 48-WFQFN 裸露焊盘
包装: 管件
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
Pin Description (continued)
PIN
9
NAME
STA_B_2
FUNCTION
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
State A State B Digital Attenuator
Logic = 0
Logic = 1
Logic = 0
Logic = 0
Preprogrammed State 1
Preprogrammed State 2
10
STA_A_2
Logic = 0
Logic = 1
Logic = 1
Logic = 1
Preprogrammed State 3
Preprogrammed State 4
11
14
15
16
17
18
19
20
21
22
23
24
26
27
D_ATT_IN_2
D0_2
D1_2
D2_2
D3_2
D_ATT_OUT_2
D4_2
A_ATT_IN_2
DA_SP
A_VCTL_2
A_ATT_OUT_2
V CC_AMP_2
AMP_IN_2
PD_2
5-Bit Digital Attenuator Input (50 I ), Path 2. Requires a DC-blocking capacitor.
1dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
2dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
4dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
8dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
5-Bit Digital Attenuator Output (50 I ), Path 2. Requires a DC-blocking capacitor. Connect to
A_ATT_IN_2 through a 1000pF capacitor.
16dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
Analog Attenuator Input (50 I ), Path 2. Requires a DC-blocking capacitor. Connect to
D_ATT_OUT_2 through a 1000pF capacitor.
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to logic 1 to select serial control.
Set DA_SP to logic 0 to select parallel control.
Analog Attenuator Voltage Control Input, Path 2. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
Analog Attenuator Output (50 I ), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
Driver Amplifier Input (50 I ), Path 2. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_2 through a 1000pF capacitor.
Power-Down, Path 2. See Table 2 for operation details.
29
AMP_OUT_2 Driver Amplifier Output (50 I ), Path 2. Connect a pullup inductor from AMP_OUT_2 to V CC_.
30
31
REG_OUT
AMPSET
Regulator Output. Bypass with 1 F F capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V operation on pins
V CC_AMP_1 and V CC_AMP_2 . Set to logic 0 for 5V operation.
32
AMP_OUT_1 Driver Amplifier Output (50 I ), Path 1. Connect a pullup inductor from AMP_OUT_1 to V CC_.
34
35
37
38
39
PD_1
AMP_IN_1
V CC_AMP_1
A_ATT_OUT_1
A_VCTL_1
Power-Down, Path 1. See Table 2 for operation details.
Driver Amplifier Input (50 I ), Path 1. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_1 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
Analog Attenuator Output (50 I ), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
Analog Attenuator Voltage Control Input, Path 1. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
16
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