参数资料
型号: MAX260BEWG+
厂商: Maxim Integrated Products
文件页数: 4/26页
文件大小: 0K
描述: IC FILTER ACT MPU PROG 24-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
滤波器类型: 通用开关电容器
频率 - 截止或中心: 7.5kHz
滤波器数: 2
滤波器阶数: 2nd
电源电压: 4.74 V ~ 12.6 V,±2.37 V ~ 6.3 V
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
12
______________________________________________________________________________________
Detailed Description
f0 and Q Programming
Figure 3 shows a block diagram of the MAX260. Each
second-order filter section has its own clock input and
independent f0 and Q control. The actual center fre-
quency is a function of the filter's clock rate, 6-bit f0
control word (see Table 2), and operating mode. The Q
of each section is also set by a separate programmed
input (see Table 3). This way, each half of a MAX260/
MAX261/MAX262 is tuned independently so that com-
plex filter polynomials can be realized. Equations that
convert program code numbers to fCLK/f0 and Q values
are listed in the notes beneath Tables 2 and 3.
Oscillator and Clock Inputs
The clock circuitry of the MAX260/MAX261/MAX262
can operate with a crystal, resistor-capacitor (RC) net-
work, or an external clock generator as shown in Figure
4. If an RC oscillator is used, the clock rate, fCLK, nomi-
nally equals 0.45/RC.
The duty cycle of the clock at CLKA and CLKB is unim-
portant because the input is internally divided by 2 to
generate the sampling clock for each filter section. It is
important to note that this internal division also halves
the sample rate when considering aliasing and other
sampled system phenomenon.
Microprocessor Interface
f0, Q, and mode-selection data are stored in internal
program memory. The memory contents are updated
by writing to addresses selected by A0–A3. D0, and D1
are the data inputs. A map of the memory locations is
shown in Table 4. Data is stored in the selected
address on the rising edge of WR. Address and data
inputs are TTL and CMOS compatible when the filter is
powered from ±5V. With other power supply voltages,
CMOS logic levels should be used. Interface timing is
shown in Figure 5. Note: Clock inputs CLKA and CLKB
have no relation to the digital interface. They control the
switched-capacitor filter sample rate only.
Some noise may be generated on the filter outputs by
transitions at the logic inputs. If this is objectionable,
fCLK/f0 RATIO
MAX260/MAX261
MAX262
PROGRAM CODE
MODES 1,3,4
MODE 2
MODES 1,3,4
MODE 2
N
F5
F4
F3
F2
F1
F0
172.79
122.18
113.10
79.97
46
101110
174.36
123.29
114.66
81.08
47
101111
175.93
124.40
11624
82.19
48
110000
177.50
125.51
117.81
83.30
49
110001
179.07
126.62
119.38
84.41
50
110010
180.64
127.73
120.95
85.53
51
110011
182.21
128.84
122.52
86.64
52
110100
183.78
129.96
124.09
87.75
53
110101
185.35
131.07
125.66
88.86
54
110110
186.92
132.18
127.23
89.97
55
110111
188.49
133.29
128.81
91.08
56
111000
190.07
134.40
130.38
92.19
57
111001
191.64
135.51
131.95
93.30
58
111010
193.21
136.62
133.52
94.41
59
111011
194.78
137.73
135.09
95.52
60
111100
196.35
138.84
136.66
96.63
61
111101
197.92
139.95
138.23
97.74
62
111110
199.49
141.06
139.80
98.85
63
111111
Table 2. fCLK/f0 Program Selection Table (continued)
Note 1: For the MAX260/MAX261, fCLK/f0 = (64 + N)
π / 2 in modes 1, 3, and 4, where N varies from 0 to 63.
Note 2: For the MAX262, fCLK/f0 = (26 s N)
π / 2 in modes 1, 3, and 4, where N varies 0 to 63.
Note 3: In mode 2, all fCLK/f0 ratios are divided by
√2. The functions are then:
MAX260/MAX261 fCLK/f0 = 1.11072 (64 + N), MAX262 fCLK/f0 = 1.11072 (26 + N)
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