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| 型号： | MAX261BEWG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/26页 |
| 文件大小： | 0K |
| 描述： | IC FILTER ACT MPU PROG 24-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 滤波器类型： | 通用开关电容器 |
| 频率 - 截止或中心： | 57kHz |
| 滤波器数： | 2 |
| 滤波器阶数： | 2nd |
| 电源电压： | 4.74 V ~ 12.6 V，±2.37 V ~ 6.3 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (for V± = ±2.5V ±5%)
(V+ = +2.37V, V- = -2.37V, CLKA = CLKB = ±2.5V 250kHz for the MAX260 and 1MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for
MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f0 Center Frequency Range
(Note 7)
Maximum Clock Frequency
(Note 7)
MAX26XA
±0.1
1
fCLK/f0 Ratio Error
(Notes 1, 8)
Q = 8
MAX26XB
±0.1
2
%
MAX260A
±2
±6
Q = 8
fCLK/f0 = 199.49
MAX260B
±2
±10
MAX261A
±2
±6
fCLK/f0 = 199.49
MAX261B
±2
±10
MAX262A
±2
±6
Q Accuracy (deviation from ideal
continuous filter)
(Notes 2, 8)
fCLK/f0 = 139.80
MAX262B
±2
±10
%
Output Signal Swing
All Outputs (Note 6)
±2
V
Power Supply Current
CMOS Level Logic Inputs (Note 5)
7
mA
Shutdown Current
CMOS Level Logic Inputs (Note 5)
0.35
mA
Note 1: fCLK/f0 accuracy is tested at 199.49 on the MAX260/MAX261, and at 139.8 on the MAX262.
Note 2: Q accuracy tested at Q = 8, 32, and 64. Q of 32 and 64 tested at 1/2 stated clock frequency.
Note 3: The offset voltage is specified for the entire filter. Offset is virtually independent of Q and fCLK/f0 ratio setting. The test clock
frequency for mode 3 is 175kHz for the MAX260 and 750kHz for the MAX261/MAX262.
Note 4: Output noise is measured with an RC output smoothing filter at 4 f0 to remove clock feedthrough.
Note 5: TTL logic levels are: HIGH = 2.4V, LOW = 0.8V. CMOS logic levels are: HIGH = 5V, LOW = 0V. Power supply current is typi-
cally 4mA higher with TTL logic and clock input levels.
Note 6: On the MAX260 only, the HP output signal swing is typically 0.75V less than the LP or BP outputs.
Note 7: At ±2.5V supplies, the f0 range and maximum clock frequency are typically 75% of values listed in Table 1.
Note 8: fCLK/f0 and Q accuracy are a function of the accuracy of internal capacitor ratios. No increase in error is expected at ±2.5V
as compared to ±5V; however, these parameters are only tested to the extent indicated by the MIN or MAX limits.
INTERFACE SPECIFICATIONS (Note 9)
(V+ = +5V, V+ = -5V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WR Pulse Width
tWR
250
150
ns
Address Setup
tAS
25
ns
Address Hold
tAH
0ns
Data Setup
tDS
100
50
ns
Data Hold
tDH
10
0
ns
Logic Input High
VIH
WR, D0, D1, A0–A3, CLKA, CLKB
TA =TMIN to TMAX
2.4
V
Logic Input Low
VIL
WR, D0, D1, A0–A3, CLKA, CLKB
TA =TMIN to TMAX
0.8
V
10
60
Input Leakage Current
IIN
WR, D0, D1, A0–A3, CLKB
CLKA
TA =TMIN to TMAX
6A
Input Capacitance
CIN
WR, D0, D1, A0–A3, CLKA, CLKB
15
pF
Note 9: Interface timing specifications are guaranteed by design and are not subject to test.
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