参数资料
型号: MAX2769BETI/V+T
厂商: Maxim Integrated
文件页数: 20/27页
文件大小: 0K
描述: IC RCVR GPS UNIVERSAL 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 1575.42MHz
调制或协议: GPS
应用: GPS
电流 - 接收: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX2769B
Universal GPS Receiver
Table 8. Configuration 2 (Address: 0001)
DEFAULT
DATA BIT
LOCATION
VALUE
DESCRIPTION
(PGM = 0)
IQEN
27
0
I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I
channel only.
AGC gain reference value expressed by the number of MSB counts (magnitude bit
GAINREF
26:15
170d
density). 10101010 = 234 magnitude bit density reference, 1010100 = 84 magnitude bit
density reference, 100111010 = 314 magnitude bit density reference.
RESERVED
AGCMODE
FORMAT
BITS
DRVCFG
RESERVED
RESERVED
DIEID
14:13
12:11
10:9
8:6
5:4
3
2
1:0
00
00
01
010
00
1
0
00
Reserved.
AGC mode control. Set D12:D11 = 00: independent I and Q; 01: reserved; 10: gain is set
directly from the serial interface by GAININ; 11: reserved.
Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X:
two’s complement binary.
Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: reserved; 010: 2 bits;
011: reserved, 100: 3 bits.
Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: reserved; 1X: analog
outputs.
Identifies a version of the IC.
Table 9. Configuration 3 (Address: 0010)
DEFAULT
DATA BIT
LOCATION
VALUE
DESCRIPTION
(PGM = 0)
PGA gain value programming from the serial interface in steps of dB per LSB. 000000 =
GAININ
27:22
111010
PGA gain set to 0dB, 101011 = 42dB, 101100 = 43dB, 101110 = 45dB, 111010 = 57dB,
111111 = 62dB.
RESERVED
HILOADEN
RESERVED
RESERVED
RESERVED
RESERVED
FHIPEN
RESERVED
RESERVED
RESERVED
21
20
19
18
17
16
15
14
13
12
1
0
1
1
1
1
1
1
1
0
Set 1 to enable the output driver to drive high loads.
Highpass coupling enable. Set 1 to enable the highpass coupling between the filter
and PGA, or 0 to disable the coupling.
DSP interface for serial streaming of data enable. This bit configures the IC such that the
STRMEN
11
0
DSP interface is inserted in the signal path. Set 1 to enable the interface or 0 to disable
the interface.
Maxim Integrated
20
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