参数资料
型号: MAX2769BETI/V+T
厂商: Maxim Integrated
文件页数: 21/27页
文件大小: 0K
描述: IC RCVR GPS UNIVERSAL 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 1575.42MHz
调制或协议: GPS
应用: GPS
电流 - 接收: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX2769B
Universal GPS Receiver
Table 9. Configuration 3 (Address: 0010) (continued)
DEFAULT
DATA BIT
LOCATION
VALUE
DESCRIPTION
(PGM = 0)
STRMSTART
STRMSTOP
RESERVED
STRMBITS
STAMPEN
10
9
8:6
5:4
3
0
0
111
01
1
The positive edge of this command enables data streaming to the output. It also enables
clock, data sync, and frame sync outputs.
The positive edge of this command disables data streaming to the output. It also
disables clock, data sync, and frame sync outputs.
Number of bits streamed. D5:D4 = 00: reserved; 01: 1 MSB, 1 LSB; 10: reserved, Q
MSB; 11: 1 MSB, 1 LSB, Q MSB, Q LSB.
The signal enables the insertion of the frame number at the beginning of each frame. If
disabled, only the ADC data is streamed to the output.
This signal enables the output of the time sync pulses at all times when streaming is
TIMESYNCEN
2
1
enabled by the STRMEN command. Otherwise, the time sync pulses are available only
when data streaming is active at the output, for example, in the time intervals bound by
the STRMSTART and STRMSTOP commands.
This control signal enables the sync pulses at the DATASYNC output. Each pulse is
DATSYNCEN
1
0
coincident with the beginning of the 16-bit data word that corresponds to a given output
bit.
STRMRST
0
0
This command resets all the counters irrespective of the timing within the
stream cycle.
Table 10. PLL Configuration (Address: 0011)
DEFAULT
DATA BIT
LOCATION
VALUE
DESCRIPTION
(PGM = 0)
RESERVED
RESERVED
RESERVED
REFOUTEN
RESERVED
27
26
25
24
23
1
0
0
1
1
Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer.
Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2;
REFDIV
22:21
11
01: clock frequency = XTAL frequency/4; 10: clock frequency = XTAL frequency/2;
11: clock frequency = XTAL.
IXTAL
RESERVED
LDMUX
Maxim Integrated
20:19
18:14
13:10
01
10000
0000
Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: reserved; 01: buffer
normal current; 10: reserved; 11: oscillator high current.
PLL lock-detect enable.
21
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