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| 型号： | MAX2769EVKIT+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 20/23页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MAX2769 |
| 其它有关文件： | Automotive Product Guide |
| 标准包装： | 1 |
| 类型： | GNSS 接收器 |
| 适用于相关产品： | MAX2769 |
| 已供物品： | 模块 |
MAX2769
Universal GPS Receiver
Table 9. PLL Configuration (Address: 0011)
DATA BIT
VCOEN
IVCO
—
REFOUTEN
—
LOCATION
27
26
25
24
23
DEFAULT
VALUE
1
0
0
1
1
DESCRIPTION
VCO enable. Set 1 to enable the VCO or 0 to disable VCO.
VCO current-mode selection. Set 1 to program the VCO in the low-current mode or
0 to program in the normal mode.
Reserved.
Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer.
Reserved.
Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2; 01:
REFDIV
22:21
11
clock frequency = XTAL frequency / 4; 10: clock frequency = XTAL frequency / 2; 11:
clock frequency = XTAL.
Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: oscillator normal
IXTAL
20:19
01
current; 01: buffer normal current; 10: oscillator medium current; 11: oscillator high
current.
20
XTALCAP
LDMUX
ICP
PFDEN
—
CPTEST
INT_PLL
PWRSAV
—
—
18:14
13:10
9
8
7
6:4
3
2
1
0
10000
0000
0
0
0
000
1
0
0
0
Digital XTAL load cap programming.
LD pin output selection. Set D13:D10 = 0000: PLL lock-detect signal.
Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA.
Set 0 for normal operation or 1 to disable the PLL phase frequency detector.
Reserved.
Charge-pump test. Set D6:D4 = 000: normal operation; X10: pump up; X01 = pump
down; 100 = high impedance; 111: both up and down on.
PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL.
PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable.
Reserved.
Reserved.
Maxim Integrated
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