参数资料
型号: MAX2769EVKIT+
厂商: Maxim Integrated
文件页数: 21/23页
文件大小: 0K
描述: KIT EVAL FOR MAX2769
其它有关文件: Automotive Product Guide
标准包装: 1
类型: GNSS 接收器
适用于相关产品: MAX2769
已供物品: 模块
MAX2769
Universal GPS Receiver
Table 10. PLL Integer Division Ratio (Address 0100)
DATA BIT
NDIV
RDIV
LOCATION
27:13
12:3
2:0
DEFAULT
VALUE
1536d
16d
000
PLL integer division ratio.
PLL reference division ratio.
Reserved.
DESCRIPTION
Table 11. PLL Division Ratio (Address 0101)
DATA BIT
FDIV
LOCATION
27:8
7:0
DEFAULT
VALUE
80000h
01110000
PLL fractional divider ratio.
Reserved.
DESCRIPTION
Table 12. DSP Interface (Address 0110)
DATA BIT
LOCATION
DEFAULT
VALUE
DESCRIPTION
This word defines the frame number at which to start streaming. This mode is active
when streaming mode is enabled by a command STRMEN, but a command
FRAMECOUNT
27:0
8000000h
STRMSTART is not received. In this case, the frame counter is reset upon the assertion
of STRMEN, and it begins its count. When the frame number reaches the value defined
by FRMCOUNT, the streaming begins.
Table 13. Clock Fractional Division Ratio (Address 0111)
DATA BIT
L_CNT
M_CNT
FCLKIN
ADCCLK
SERCLK
MODE
LOCATION
27:16
15:4
3
2
1
0
DEFAULT
VALUE
256d
1563d
0
0
1
0
DESCRIPTION
Sets the value for the L counter.
Sets the value for the M counter.
Fractional clock divider. Set 1 to select the ADC clock to come from the fractional
clock divider, or 0 to bypass the ADC clock from the fractional clock divider.
ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come
from the reference divider/multiplier.
Serializer clock selection. Set 0 to select the serializer clock output to come from the
reference divider/multiplier.
DSP interface mode selection.
Table 14. Test Mode 1 (Address 1000)
Table 15. Test Mode 2 (Address 1001)
DATA BIT
LOCATION
27:0
DEFAULT
VALUE
1E0F401
DESCRIPTION
Reserved.
DATA BIT
LOCATION
27:0
DEFAULT
VALUE
14C0402
DESCRIPTION
Reserved.
Maxim Integrated
21
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