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参数资料
| 型号： | MAX2831ETM+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 27/34页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 2.4GHZ-2.5GHZ 48TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 2.4GHz ~ 2.5GHz |
| 数据传输率 - 最大： | 54Mbps |
| 调制或协议： | 802.11b/g |
| 应用： | WLAN |
| 功率 - 输出： | 18.5dBm |
| 灵敏度： | -76dBm |
| 电源电压： | 2.7 V ~ 3.6 V |
| 电流 - 接收： | 62mA |
| 电流 - 传输： | 209mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
Programmable Registers and
3-Wire SPI-Interface
The MAX2831/MAX2832 include 16 programmable, 18-
bit registers. The 14 most significant bits (MSBs) are
used for register data. The 4 least significant bits
(LSBs) of each register contain the register address.
See Table 14 for a summary of the registers and rec-
ommended register settings.
Register data is loaded through the 3-wire SPI/
MICROWIRE ?-compatible serial interface. Data is
MICROWIRE is a trademark of National Semiconductor Corp.
Table 14. Recommended Register Settings*
shifted in MSB first and is framed by CS . When CS is
low, the clock is active, and data is shifted with the ris-
ing edge of the clock. When CS transitions high, the
shift register is latched into the register selected by the
contents of the address bits. See Figure 2. Only the last
18 bits shifted into the device are retained in the shift
register. No check is made on the number of clock
pulses. For programming data words less than 14 bits
long, only the required data bits and the address bits
need to be shifted, resulting in faster Rx and Tx gain
control where only the LSBs need to be programmed.
REGISTER
D13
D12
D11
D10
D9
D8
DATA
D7 D6
D5
D4
D3
D2
D1
D0
ADDRESS
(A3:A0)
TABLE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
* The power-on register settings are not production tested. Recommended register settings must be loaded after V CC is supplied.
DIN
BIT 1
BIT 2
BIT 15
BIT 16
BIT 23
BIT 24
SCLK
t DS
t CL
t CH
t CS1
CS
t CSO
t CSS
t DH
t CSH
t CSW
Figure 2. 3-Wire SPI Serial-Interface Timing Diagram
______________________________________________________________________________________
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