参数资料
型号: MAX2851ITK+T
厂商: Maxim Integrated
文件页数: 24/37页
文件大小: 0K
描述: TRANSMITTER MIMO 5GHZ 5CH 68TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 4.9GHz ~ 5.9GHz
数据传输率 - 最大: 54Mbps
调制或协议: *
应用: *
功率 - 输出: -3dBm
电源电压: 2.7 V ~ 3.6 V
电流 - 接收: *
电流 - 传输: *
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -25°C ~ 85°C
封装/外壳: 68-TQFN 裸露焊盘
包装: 带卷 (TR)
5GHz, 5-Channel MIMO Receiver
RF Loopback Mode
In RF loopback mode, part of the Rx and Tx circuit
blocks except the LNA are powered on and active. The
transmitter I/Q input signal is upconverted to RF, and the
output of the transmitter is fed to the receiver downcon-
verter input. Output signals are delivered to all receiver
baseband I/Q outputs. The I/Q lowpass filters in the
transmitter signal path are bypassed.
Baseband Loopback Mode
In baseband loopback mode, part of the Rx and Tx
baseband circuit blocks are powered and active. The
transmitter I/Q input signal is routed to the receiver low-
pass filter input. Output signals are delivered to receiver 5
baseband I/Q outputs.
Power-On Sequence
Set the ENABLE pin to V CC for 2ms to start the crystal
oscillator. Program all SPI addresses according to rec-
ommended values. Set SPI Main address 0 D[4:2] from
000 to 001 to engage standby mode. To lock the LO
frequency, the user can set SPI in order of Main address
15, Main address 16, and then Main address 17 to trig-
ger VCO sub-band autoacquisition; the acquisition takes
2ms. After the LO frequency is locked, set SPI Main
address 0 D[4:2] = 010 and 011 for Rx and Tx operating
modes, respectively. Before engaging to Rx mode, set
Main address 5 D1 = 1 to allow fast DC-offset settling.
After engaging to Rx mode and the Rx baseband DC
offset settles, the user can set Main address 5 D1 = 0 to
complete Rx DC-offset cancellation.
Programmable Registers and
4-Wire SPI Interface
The MAX2851 includes 60 programmable 16-bit reg-
isters. The most significant bit (MSB) is the read/write
selection bit (R/W in Figure 1). The next 5 bits are register
address (A[4:0] in Figure 1). The 10 least significant bits
(LSBs) are register data (D[9:0] in Figure 1). Register
data is loaded through the 4-wire SPI/MICROWIRE K -
compatible serial interface. MSB of data at the DIN pin
is shifted in first and is framed by CS . When CS is low,
the clock is active and input data is shifted at the rising
edge of the clock at the SCLK pin. At CS rising edge,
the 10-bit data bits are latched into the register selected
by the address bits. See Figure 1. To support more than
a 32-register address using a 5-bit-wide address word,
the bit 0 of address 0 is used to select whether the 5-bit
address word is applied to the main address or local
address. There is no power-on SPI register self-reset
functionality in the MAX2851; the user must program all
register values after power-up. During the read mode,
register data selected by address bits is shifted out to
the DOUT pin at the falling edges of the clock.
MICROWIRE is a trademark of National Semiconductor Corp.
t CSW
CS
SCLK
t CSO
t CSS
t CSH
t CS1
t DS
t DH
t CH
t CL
DIN
(SPI WRITE)
DIN
(SPI READ)
R/W
R/W
A4
A4
A0
A0
D9
D9
D0
D0
DON’T CARE
DON’T CARE
t D
DOUT
(SPI READ)
DON’T CARE
D9
D0
DON’T CARE
Figure 1. 4-Wire SPI Serial-Interface Timing Diagram
24
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