参数资料
型号: MAX2870EVKIT#
厂商: Maxim Integrated
文件页数: 12/24页
文件大小: 0K
描述: EVAL KIT MAX2870
标准包装: 1
系列: *
MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
Detailed Description
4-Wire Serial Interface
The MAX2870 serial interface contains five write-only and
one read-only 32-bit registers. The 29 most-significant
bits (MSBs) are data, and the three least-significant bits
(LSBs) are the register address. Register data is loaded
MSB first through the 4-wire serial interface (SPI). When
LE is logic-low, the logic level at DATA is shifted at the
rising edge of CLK. At the rising edge of LE, the 29 data
bits are latched into the register selected by the address
bits. The user must program all register values after
power-up.
Register programming order should be address 0x05,
0x04, 0x03, 0x02, 0x01, and 0x00. Several bits are dou-
ble buffered to update the settings at the same time. See
the register descriptions for double buffered settings.
Register 0x06 can be read back through MUX_OUT.
The user must set MUX = 1100. To begin the read
sequence, set LE to logic-low, send 32 periods of CLK,
and set LE to logic-high. While the CLK is running, the
DATA pin can be held at logic-high or logic-low for 29
clocks, but the last 3 bits must be 110 to indicate regis-
ter 6. Then finally, send 1 period of the clock. The MSB
of register 0x06 appears on the falling edge of the next
clock and continues to shift out for the next 29 clock
cycles (Figure 2). After the LSB of register 0x06 has
been read, the user can reset MUX = 0000.
Power Modes
The MAX2870 can be put into low-power mode by set-
ting SHDN = 1 (register 2, bit 5) or by setting the CE pin
to logic-low.
LE
t LES
t CP
t LEH
t LEW
t CL
CLK
t CH
t DS
t DH
I DATA
BIT31
BIT30
BIT29
BIT1
BIT0
Figure 1. SPI Timing Diagram
DATA
LE
CLK
DON’T CARE
t MH
1
29
30
31
32
33
34
35
36
MUX_OUT
t MS
Figure 2. Initiating Readback
Maxim Integrated
12
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