参数资料
型号: MAX2870EVKIT#
厂商: Maxim Integrated
文件页数: 16/24页
文件大小: 0K
描述: EVAL KIT MAX2870
标准包装: 1
系列: *
MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
Register and Bit Descriptions
The operating mode of the device is controlled by five on-chip registers.
Defaults are not guaranteed upon power-up and are provided for reference only. All reserved bits should only be written
with default values. In low-power mode the register values are retained.
Table 4. Register 0 (Address: 000, Default: 007D0000 HEX )
BIT LOCATION
31
30:15
BIT ID
INT
N[15:0]
NAME
Int-N or Frac-N
Mode Control
Integer Division
Value
DEFINITION
0 = Enables the fractional-N mode
1 = Enables the integer-N mode
The LDF bit must also be set to the appropriate mode.
Sets integer part (N-divider) of the feedback divider factor. All integer
values from 16 to 65,535 are allowed for integer mode. Integer values
from 19 to 4,091 are allowed for fractional mode.
Sets fractional value:
000000000000 = 0 (see F0I bit description)
14:3
FRAC[11:0]
Fractional
Division Value
000000000001 = 1
----
111111111110 = 4094
111111111111 = 4095
2:0
ADDR[2:0]
Address Bits
Register address bits
Table 5. Register 1 (Address: 001, Default: 2000FFF9 HEX )
BIT LOCATION
BIT ID
NAME
DEFINITION
Sets charge-pump output clamp mode.
31
CPOC
CP Output
Clamp
0 = Disables clamping of the CP output when the CP is off
1 = Enables the clamping of the CP output when the CP is off (improved
integer-N in-band phase noise)
Sets CP linearity mode.
00 = Disables the CP linearity mode (integer-N mode)
30:29
CPL[1:0]
CP Linearity
01 = Enables the CP linearity mode (frac-N mode)
10 = Reserved
11 = Reserved
Sets charge-pump test modes.
Charge Pump
00 = Normal mode
28:27
CPT[1:0]
Test
01 = Reserved
10 = Force CP into source mode
11 = Force CP into sink mode
Sets phase value. See the Phase Shift Mode section.
000000000000 = 0
26:15
P[11:0]
Phase Value
000000000001 = 1 (recommended)
-----
111111111111 = 4095
Maxim Integrated
16
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