参数资料
型号: MAX3273ETG+T
厂商: Maxim Integrated
文件页数: 9/18页
文件大小: 0K
描述: IC LASR DRVR 2.7GBPS 3.6V 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管驱动器(光纤)
数据速率: 2.7Gbps
通道数: 1
电源电压: 3.14 V ~ 3.6 V
电流 - 电源: 30mA
电流 - 调制: 60mA
电流 - 偏置: 100mA
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
安装类型: 表面贴装
+3.3V, 2.5Gbps Low-Power Laser Driver
optical output ringing and duty-cycle distortion. Refer to
Maxim application note HFAN 02.0, Interfacing Maxim
Laser Drivers with Laser Diodes, for more information.
At the data rate of 2.5Gbps, any capacitive load at the
cathode of a laser diode degrades the optical output
performance. Because the BIAS output is directly con-
nected to the laser cathode, the parasitic capacitance
associated with this pin is minimized by using an induc-
tor to isolate the BIAS pin from the laser cathode.
Automatic Power Control (APC)
To maintain constant average optical power, the
MAX3273 incorporates an APC loop to compensate for
the changes in laser threshold current over temperature
and lifetime. A back-facet photodiode mounted in the
laser package is used to convert the optical power into
a photocurrent. The APC loop adjusts the laser bias
current so that the monitor current is matched to a ref-
erence current set by R APCSET . The time constant of
the APC loop is determined by an external capacitor
(C APCFILT ). To minimize the pattern-dependent jitter
associated with the APC loop-time constant, and to
guarantee loop stability, the recommended value for
C APCFILT is 0.01μF.
When the APC loop is functioning, the maximum allow-
able bias current is set by an external resistor, R BIASMAX .
An APC failure flag ( FAIL ) is asserted low when the bias
current can no longer be adjusted to achieve the desired
average optical power.
APC closed-loop operation requires the user to set three
currents with external resistors connected between
ground and BIASMAX, MODSET, and APCSET (see
Figure 3). Detailed guidelines for these resistor settings
are described in the Design Procedure section.
Open-Loop Operation
If necessary, the MAX3273 is fully operational without
APC. To disable the APC loop, ground the APCFILT1
pin. In this case, the laser current is directly set by two
external resistors connected from ground to BIASMAX
and MODSET. See the Design Procedure section for
more details on open-loop operation.
Output Enable
The MAX3273 incorporates a TTL/CMOS input to
enable the output. When EN is low, the modulation and
bias outputs are enabled. When EN is high or floating,
both the bias and modulation currents are off. The typi-
cal enable time is 364ns, and the typical disable time is
27ns when the bias is operated open loop.
Slow-Start
For laser safety reasons, the MAX3273 incorporates a
slow-start circuit that provides a delay of 364ns for
enabling a laser diode.
APC Failure Monitor
The MAX3273 provides an APC failure monitor
(TTL/CMOS) to indicate an APC loop tracking failure.
FAIL is asserted low when the APC loop no longer can
regulate the bias current to maintain the desired moni-
tor diode current. FAIL asserts low when the APC loop
is disabled.
Short-Circuit Protection
The MAX3273 provides short-circuit protection for the
modulation and bias current sources. If BIASMAX,
MODSET, or APCSET is shorted to ground, the bias
and modulation output turns off.
Design Procedure
When designing a laser transmitter, the optical output
usually is expressed in terms of average power and
extinction ratio. Table 1 gives relationships helpful in
converting between the optical average power and the
modulation current. These relationships are valid if the
mark density and duty cycle of the optical waveform
are 50%.
Programming the Modulation Current
For a given laser power (P AVG ), slope efficiency ( η ), and
extinction ration (r e ), the modulation current can be cal-
culated using Table 1. See the I MOD vs. R MODSET
graph in the Typical Operating Characteristics and
select the value of R MODSET that corresponds to the
required current at +25°C. The equation below provides
a derivation of the modulation current using Table 1.
P AVE r e ? 1
η
r e + 1
Optional Data Input Latch
To minimize jitter in the input data, connect a synchro-
nous differential clock signal to the CLK+ and CLK-
inputs. When the LATCH control input is tied high, the
input data is retimed on the rising edge of CLK+. If
LATCH is tied low or left floating, the retiming function is
disabled and the input data is directly connected to the
output stage. When this latch function is not used, con-
nect CLK+ to V CC and leave CLK- unconnected.
I MOD = 2 ×
×
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