参数资料
型号: MAX3349EAEBE+T
厂商: Maxim Integrated Products
文件页数: 17/17页
文件大小: 0K
描述: IC TXRX USB 2.0 FS 16-UCSP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 收发器
驱动器/接收器数: 1/1
规程: USB 2.0
电源电压: 4 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 16-WFBGA,CSPBGA
供应商设备封装: 16-UCSP(2x2)
包装: 带卷 (TR)
MAX3349EA
USB 2.0 Full-Speed Transceiver with UART
Multiplexing Mode
_______________________________________________________________________________________
9
Detailed Description
The MAX3349EA ±15kV ESD-protected, USB transceiver
provides a full-speed USB interface to a microprocessor or
ASIC. The device supports enumeration, suspend, and
VBUS detection. A special UART multiplexing mode routes
external UART signals (Rx and Tx) to D+ and D-, allowing
the use of a shared connector to reduce cost and part count
for mobile devices.
The UART interface allows mobile devices such as PDAs,
cellular phones, and digital cameras to use either UART or
USB signaling through the same connector. The
MAX3349EA features a separate UART voltage supply
input. The MAX3349EA supports a maximum UART
baud rate of 921kbaud.
Upon connection to a USB host, the MAX3349EA
enters USB mode and provides a full-speed USB 2.0
compliant interface through VP, VM, RCV, and OE. The
MAX3349EA features internal series resistors on D+
and D-, and an internal 1.5k
pullup resistor to D+ to
allow the device to logically connect and disconnect
from the USB bus while plugged in. A suspend mode is
provided for low-power operation. D+ and D- are pro-
tected from electrostatic discharge (ESD) up to ±15kV.
To ensure full ±15kV ESD protection, bypass VBUS to
OE
VP/VM
tPLZ_SE
tPZL_SE
tPHZ_SE
tPZH_SE
D+/D- CONNECTED TO GND,
VP/VM CONNECTED
TO PULLUP
D+/D- CONNECTED TO +3V,
VP/VM CONNECTED
TO PULLDOWN
OE
Figure 5. Receiver Enable and Disable Timing
MAX3349EA
1. ENABLE TIME (D+/D-)
MEASUREMENT
D+/D-
TEST
POINT
CL
50pF
15k
2. VP/VM TO D+/D-
PROPAGATION DELAY
3. D+/D- RISE/FALL TIMES
Figure 7. Test Circuit for Enable Time, Transmitter Propagation
Delay, and Transmitter Rise/Fall Time
MAX3349EA
TEST
POINT
CL
15pF
RCV/VP/VM
1. D+/D- TO RCV/VM/VP
PROPAGATION DELAYS
Figure 8. Test Circuit for Receiver Propagation Delay
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
RD
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 9. Human Body ESD Test Model
Timing Diagrams (continued)
MAX3349EA
1. DISABLE TIME (D+/D-)
MEASUREMENT
V = 0 FOR tPHZ
V = VTRM FOR tPLZ
D+/D-
TEST
POINT
CL
50pF
220
Figure 6. Test Circuit for Disable Time
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