参数资料
型号: MAX3362EKA#TG16
厂商: Maxim Integrated Products
文件页数: 12/14页
文件大小: 0K
描述: IC TXRX RS485/422 SGL SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 收发器
驱动器/接收器数: 1/1
规程: RS422,RS485
电源电压: 3.14 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
其它名称: MAX3362EKA#TG16DKR
MAX3362
3.3V, High-Speed, RS-485/RS-422 Transceiver in
SOT Package
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
DESCRIPTION
1RO
Receiver Output. RO is high if the receiver input differential (A-B)
≥ 200mV and the receiver is enabled
(RE is low). RO is low if the receiver input differential (A-B)
≤ -200mV and the receiver is enabled.
2
RE
Receiver Output Enable. Driving RE low enables RO. RO is high impedance when RE is high. Drive RE
high and DE low (disable both receiver and driver outputs) to enter low-power shutdown mode.
3DE
Driver Output Enable. Driving DE high enables driver outputs. These outputs are high impedance
when DE is low. Drive RE high and DE low (disable both receiver and driver outputs) to enter low-
power shutdown mode.
4DI
Driver Input. Driving DI low forces the noninverting output low and inverting output high, when the driver is
enabled (DE is high). Driving DI high forces the noninverting output high and inverting output low.
5
GND
Ground
6
A
Noninverting Receiver Input and Noninverting Driver Output
7
B
Inverting Receiver Input and Inverting Driver Output
8VCC
Supply Voltage. VCC = 3.3V ±5%. Bypass VCC to GND with a 0.1F capacitor.
OUT
VCC
RL
CL
D
CL = 50pF
RL = 54
Ω
Figure 2. Driver Timing Test Circuit
0
VCC /2
VCC
B
A
tPDLH
(A+B)/2
A - B
10%
90%
tPDHL
tri
tfi
tri = 5ns
tfi = 5ns
tDF
tDR
DI
Figure 3. Driver Propagation Delay
VOD
VCC
RL/2
VOC
D
Figure 1. Driver DC Test Load
IN
OUT
tPDSL, tPDZL
tPDLZ
0.25V
VOL
0
VCC/2
VOM = (VOL + VCC) /2
VCC
RL = 500
Ω
CL = 50pF
GENERATOR
50
Ω
0 or 3V
OUT
S1
D
Figure 4. Driver Enable and Disable Times (tPDSL, tPDZL, tPDLS,
tPDLZ)
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