参数资料
型号: MAX34440ETL+T
厂商: Maxim Integrated Products
文件页数: 11/43页
文件大小: 0K
描述: IC PS MANAGER PMBUS 6CH 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 基站网络线路卡,服务器
电源电压: 2.7 V ~ 5.5 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
其它名称: 90-34440+TTR
MAX34440
PMBus 6-Channel Power-Supply Manager
Pin Description (continued)
PIN
18
19
20
22
23
24
25
26
27
28
29
30
31
32
NAME
PWM4
PSEN4
PWM3
REG18
PSEN3
PWM2
PSEN2
PWM1
PSEN1
PWM0
REG25
PSEN0
SDA
SCL
FUNCTION
PWM Margin Output #4. High impedance when the margining is disabled. A 100% duty cycle
implies this pin is continuously high.
Power-Supply Enable Output #4. Programmable through MFR_MODE for either active high or active
low and either open drain or CMOS push-pull.
PWM Margin Output #3. High impedance when the margining is disabled. A 100% duty cycle
implies this pin is continuously high.
Regulator for Low-Voltage Digital Circuitry. Bypass REG18 to V SS with 1 F F and 10nF capacitors. Do
not connect other circuitry to this pin.
Power-Supply Enable Output #3. Programmable through MFR_MODE for either active high or active
low and either open drain or CMOS push-pull.
PWM Margin Output #2. High impedance when the margining is disabled. A 100% duty cycle
implies this pin is continuously high.
Power-Supply Enable Output #2. Programmable through MFR_MODE for either active high or active
low and either open drain or CMOS push-pull.
PWM Margin Output #1. High impedance when the margining is disabled. A 100% duty cycle
implies this pin is continuously high.
Power-Supply Enable Output #1. Programmable through MFR_MODE for either active high or active
low and either open drain or CMOS push-pull.
PWM Margin Output #0. High impedance when the margining is disabled. A 100% duty cycle
implies this pin is continuously high.
Regulator for Analog Circuitry. Bypass REG25 to V SS with 30 F F to 47 F F. Do not connect other
circuitry to this pin.
Power-Supply Enable Output #0. Programmable through MFR_MODE for either active high or active
low and either open drain or CMOS push-pull.
I 2 C/SMBus-Compatible Input/Output
I 2 C/SMBus-Compatible Clock Input
SMBus Address 0 Input/Multiplexer Control Output. This dual-function pin is sampled on device
power-up to determine the SMBus address; connect a 100k I resistor from this pin to either V SS or
33
A0/MUXSEL V DD to set the address. After device power-up, this pin becomes an output that acts as voltage/
current selector for an external analog multiplexer. MUXSEL is low for voltage measurements and
high for current measurements.
Active-Low, Open-Drain Fault Input/Output. This pin is asserted when one or more of the power supplies
in a global group are shut down due to a fault condition. Also, this pin is monitored and, when it is
34
35
37
38
FAULT
CONTROL
A1/PG
ALERT
asserted, all power supplies in a global group are shut down. This pin is used to provide hardware
control for power supplies in a global group across multiple devices. This output is unconditionally
deasserted when RST is asserted or the device is power cycled. This pin has a 50 F s deglitch filter.
Device Enable. Option through ON_OFF_CONFIG for active-low or active-high power-supply control.
This pin has a 50 F s deglitch filter.
SMBus Address 1 Input/Power-Good Output. This dual-function pin is sampled on device power-up
to determine the SMBus address; connect a 100k I resistor from this pin to either V SS or V DD to set
the address. After device power-up, this pin becomes an output that transitions high when all the
enabled power supplies are above their associated POWER_GOOD_ON thresholds.
Active-Low, Open-Drain Alert Output
Maxim Integrated
11
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