参数资料
型号: MAX3541ELM+
厂商: Maxim Integrated
文件页数: 15/19页
文件大小: 0K
描述: IC TV TUNER SGL CONV 48FCLGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
产品变化通告: Product Discontinuation 20/Apr/2012
标准包装: 43
系列: *
频率: 47MHz ~ 68MHz,174MHz ~ 230MHz,470MHz ~ 862MHz
电流 - 接收: *
数据接口: PCB,表面贴装
存储容量: *
天线连接器: PCB,表面贴装
电源电压: 3.1 V ~ 3.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 48-LFLGA 裸露焊盘
供应商设备封装: 48-FCLGA-EP(7x7)
包装: 托盘
Complete Single-Conversion
Television Tuner
Write Cycle
When addressed with a write command, the MAX3541
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/ W = 0). The MAX3541 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3541 again issues an ACK if the data is suc-
cessfully written to the register. The master can contin-
ue to write data to the successive internal registers with
the MAX3541 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP con-
dition. The write cycle does not terminate until the mas-
ter issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/ W = 0). The MAX3541 issues an
ACK if the slave address byte is successfully
received. The master then sends the 8-bit address of
the first register that it wishes to read. The MAX3541
then issues another ACK. Next, the master must issue
a START condition followed by the 7 slave address
bits and a read bit (R/ W = 1). The MAX3541 issues an
ACK if it successfully recognizes its address and
begins sending data from the specified register
address starting with the most significant bit (MSB).
Data is clocked out of the MAX3541 on the rising
edge of SCL. On the 9th rising edge of SCL, the mas-
ter can issue an ACK and continue reading succes-
sive registers or it can issue a NACK followed by a
STOP condition to terminate transmission. The read
cycle does not terminate until the master issues a
STOP condition. Figure 3 illustrates an example in
which registers 0 and 1 are read back.
START
WRITE DEVICE
ADDRESS
11000[ADDR2][ADDR1]
R/W
0
ACK
WRITE REGISTER
ADDRESS
0x00
ACK
WRITE DATA TO
REGISTER 0x00
0x0E
ACK
WRITE DATA TO
REGISTER 0x01
0xD8
ACK
WRITE DATA TO
REGISTER 0x02
0xE1
ACK
STOP
Figure 2. Example: Write Registers 0 Through 2 with 0x0E, 0xD8, and 0xE1, Respectively
START
WRITE DEVICE
ADDRESS
110000[ADDR2][ADDR1]
R/W ACK
0
WRITE 1ST REGISTER
ADDRESS
0x00
ACK
START
WRITE DEVICE
ADDRESS
110000[ADDR2][ADDR1]
R/W ACK
1 —
READ DATA
REG 0
D7–D0
ACK
READ DATA
REG 1
D7–D0
NACK
STOP
Figure 3. Example: Read Data from Registers 0 and 1
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