参数资料
型号: MAX3542CLM+
厂商: Maxim Integrated
文件页数: 16/20页
文件大小: 0K
描述: IC TV TUNER SGL CONV 48LFCGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 43
系列: *
频率: 47MHz ~ 862MHz
电流 - 接收: *
数据接口: PCB,表面贴装
存储容量: *
天线连接器: PCB,表面贴装
电源电压: 3.1 V ~ 3.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 48-LFLGA 裸露焊盘
供应商设备封装: 48-FCLGA-EP(7x7)
包装: 托盘
Complete Single-Conversion
Television Tuner
Applications Information
RF Inputs
The MAX3542 features separate UHF and VHF inputs
that are matched to 75 Ω . Both inputs require a DC-
blocking capacitor. The active inputs are selected by
the input registers. In addition, the input registers
enable or disable the lowpass filter, which can be used
when the VHF input is selected. For 47MHz to 100MHz,
select the VHF_IN with the LPF filter enabled (INPT =
00). For 100MHz to 326MHz, select VHF_IN with LPF
disabled (INPT = 01). For 326MHz to 862MHz, select
UHF_IN (INPT = 10).
The separate VHF and UHF inputs can be driven from a
single RF source using a diplex filter. For diplex filter
schematic and component values, refer to the
MAX3542 Evaluation Kit data sheet.
RF Gain Control
The gain of the RF LNA can be adjusted over a typical
range of 45dB with the RFAGC pin. The RFAGC input
accepts a DC voltage from 0.5V to 3V, with 3V provid-
ing maximum gain. This pin can be controlled with the
IF power-detector output to form a closed RF gain-con-
trol loop. See the Closed-Loop RF Gain Control section
for more information.
RF Tracking Filter
The MAX3542 includes a programmable tracking filter
for each band of operation to optimize rejection of
out-of-band interference while minimizing insertion
Table 16. ROM Table
MSB
DESCRIPTION ADDRESS
loss for the desired received signal. The center fre-
quency of each tracking filter is selected by a
switched-capacitor array that is programmed by the
TFS[7:0] bits in the Tracking Filter Series Capacitor
register and the TFP[5:0] bits in the Tracking Filter
Parallel Capacitor register.
Optimal tracking filter settings for each channel vary
from part to part due to process variations. To accom-
modate part-to-part variations, each part is factory cali-
brated by Maxim. During calibration, the y-intercept
and slope for the series and parallel tracking capacitor
arrays are calculated and written into an internal ROM
table. The user must read the ROM table upon power-
up and store the data in local memory (8 bytes total) to
calculate the optimal TFS[7:0] and TFP[5:0] settings for
each channel. Table 16 shows the address and bits for
each ROM table entry. See the Interpolating Tracking
Filter Coefficients section for more information on how
to calculate the required values.
Reading the ROM Table
Each ROM table entry must be read using a two-step
process. First, the address of the ROM bits to be read
must be programmed into the TFA[3:0] bits in the
Tracking Filter ROM Address register (Table 11).
Once the address has been programmed, the data
stored in that address is transferred to the TFR[7:0] bits
in the ROM Table Data Readback register (Table 13).
The ROM data at the specified address can then be
read from the TFR[7:0] bits and stored in the micro-
processor’s local memory.
LSB
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
VHF Low
VHF Low
VHF Low
VHF High
VHF High
VHF High
UHF
UHF
UHF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
OD[2]
LS0[5]
LS1[1]
LP1[3]
HS0[1]
HP0[3]
US0[5]
US1[3]
UP0[1]
OD[1]
LS0[4]
LS1[0]
LP1[2]
HS0[0]
HP0[2]
US0[4]
US1[2]
UP0[0]
OD[0]
LS0[3]
LP0[5]
LP1[1]
HS1[3]
HP0[1]
US0[3]
US1[1]
UP1[5]
X
LS0[2]
LP0[4]
LP1[0]
HS1[2]
HP0[0]
US0[2]
US1[0]
UP1[4]
X
LS0[1]
LP0[3]
HS0[5]
HS1[1]
HP1[3]
US0[1]
UP0[5]
UP1[3]
X
LS0[0]
LP0[2]
HS0[4]
HS1[0]
HP1[2]
US0[0]
UP0[4]
UP1[2]
X
LS1[3]
LP0[1]
HS0[3]
HP0[5]
HP1[1]
US1[5]
UP0[3]
UP1[1]
X
LS1[2]
LP0[0]
HS0[2]
HP0[4]
HP1[0]
US1[4]
UP0[2]
UP1[0]
16
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