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参数资料
| 型号： | MAX3542CLM+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC TV TUNER SGL CONV 48LFCGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 43 |
| 系列： | * |
| 频率： | 47MHz ~ 862MHz |
| 电流 - 接收： | * |
| 数据接口： | PCB，表面贴装 |
| 存储容量： | * |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 3.1 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-LFLGA 裸露焊盘 |
| 供应商设备封装： | 48-FCLGA-EP（7x7） |
| 包装： | 托盘 |
Complete Single-Conversion
Television Tuner
Interpolating Tracking Filter Coefficients
The TFS[7:0] and TFP[5:0] bits must be reprogrammed
for each channel frequency to optimize performance.
The optimal settings for each channel can be calculat-
ed from the ROM table data using the equations below:
Analog (PAL) Channels:
VHF_LO Filter:
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by
connecting the IFOVLD output to the RFAGC input.
Using a 10k Ω pullup resistor on the IFOVLD pin as
shown in the Typical Application Circuit results in a
nominal control voltage range of 0.5V to 3V.
VCO and VCO Divider Selection
- 12) × f RF × 10 ]
- 14) × f RF × 10 ]
TFS = INT[ 10
TFP = INT[10
[(1.1 ×
[(0.8 ×
LS0
64
LP 0
64
+ 2.2) + (4 ×
+ 1.6) + (8 ×
LS1
16
LP1
16
-3
-3
] ? 10
]
The MAX3542 frequency synthesizer includes three
VCOs and eight VCO sub-bands to guarantee
a 2200MHz to 4400MHz VCO frequency range. The fre-
quency synthesizer also features an additional VCO
frequency divider that must be programmed to either 4,
[(1.3 ×
+ 2.5) + (4 ×
- 8) × f RF × 10 ]
] ? 10
- 3.2) × f RF × 10 - 3 ]
+ 1.6) + (1.6 ×
]
VHF_HI Filter:
:
TFS = INT[ 10
[(0.8 ×
TFP = INT[10
HS0
64
HP 0
64
HS1 -3
16
HP1
16
8, 16, or 32 by the VDIV[1:0] bits in the VCO register
based on the channel being received.
To ensure PLL lock, the proper VCO and VCO sub-
band for the channel being received must be chosen
by iteratively selecting a VCO and VCO sub-band, then
reading the LD[2:0] bits to determine if the PLL is
- 3) × f RF × 10 ]
UHF Filter:
TFS = INT[ 10
[(
US0
64
+ 3) + (2 ×
US1
64
-3
] - 20
locked. Any reading from 001 to 110 indicates the PLL
is locked. If LD[2:0] reads 000, the PLL is unlocked and
the selected VCO is at the bottom of its tuning range; a
lower VCO sub-band must be selected. If LD[2:0] reads
- 2.5) × f RF × 10 ]
TFP = INT[10
[(0.8 ×
UP0
64
+ 1 .6) + (2 ×
UP1
64
-3
] - 1 0
111, the PLL is unlocked and the selected VCO is at the
top of its tuning range; a higher VCO sub-band must be
where:
f RF = operating frequency in megahertz.
TFS = decimal value of the optimal TFS[7:0] setting
(Table 9) for the given operating frequency.
TFP = decimal value of the optimal TFP[5:0] setting
(Table 10) for the given operating frequency.
LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0,
US1, UP0, and UP1 = the decimal values of the
ROM table coefficients (Table 16).
Digital (DVB-T) channels:
Consult the factory for DVB-T coefficients.
IF Overload Detector
The MAX3542 includes a broadband IF overload detec-
tor, which provides an indication of the total power pre-
sent at the RF input. The overload-detector output voltage
is compared to a reference voltage, and the difference is
amplified. This error signal drives an open-collector tran-
sistor whose collector is connected to the IFOVLD pin,
causing the IFOVLD pin to sink current. The nominal full-
scale current sunk by the IFOVLD pin is 300μA. The
IFOVLD pin requires a 10k Ω pullup resistor to V CC .
The IF overload detector is calibrated at the factory to
attack at 0.7V P-P at the IFOUT1. Upon power-up, the
baseband processor must read OD[2:0] from the ROM
table and store it in the IFOVLD register.
selected. The VCO and VCO sub-band settings should
be progressively increased or decreased until the
LD[2:0] reading falls in the 001 to 110 range.
Due to overlap between VCO sub-band frequencies,
it is possible that multiple VCO settings can be used
to tune to the same channel frequency. System per-
formance at a given channel should be similar
between the various possible VCO settings, so it is
sufficient to select the first VCO and VCO sub-band
that provides lock.
Layout Considerations
The MAX3542 EV kit can serve as a guide for PCB lay-
out. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. The exposed paddle must be
soldered evenly to the board’s ground plane for proper
operation. Use abundant vias beneath the exposed pad-
dle for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at the central
V CC node. The V CC traces branch out from this node,
with each trace going to separate V CC pins of the
MAX3542. Each V CC pin must have a bypass capacitor
with a low impedance to ground at the frequency of
interest. Do not share ground vias among multiple con-
nections to the PCB ground plane.
______________________________________________________________________________________
17
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| MAX3542CLM+ | 功能描述:调谐器 Single-Conversion Television Tuner RoHS:否 制造商:NXP Semiconductors 功能: 噪声系数: 工作电源电压: 最小工作温度: 最大工作温度: |
| MAX3542CLM+T | 功能描述:调谐器 DVB Tuner RoHS:否 制造商:NXP Semiconductors 功能: 噪声系数: 工作电源电压: 最小工作温度: 最大工作温度: |
| MAX3542EVKIT+ | 功能描述:射频开发工具 MAX3542 Eval Kit RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| MAX3543CTL+ | 功能描述:调谐器 Broadband Analog & Digital TV Tuner RoHS:否 制造商:NXP Semiconductors 功能: 噪声系数: 工作电源电压: 最小工作温度: 最大工作温度: |
| MAX3543CTL+T | 功能描述:调谐器 Broadband Analog & Digital TV Tuner RoHS:否 制造商:NXP Semiconductors 功能: 噪声系数: 工作电源电压: 最小工作温度: 最大工作温度: |
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