参数资料
型号: MAX3600CTL+
厂商: Maxim Integrated
文件页数: 15/23页
文件大小: 0K
描述: IC LASER DVR PROJECTOR 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管驱动器
通道数: 4
电源电压: 3.3V
工作温度: 0°C ~ 70°C
封装/外壳: 40-TQFN 裸露焊盘
供应商设备封装: 40-TQFN EP
包装: 托盘
安装类型: 表面贴装
Laser Driver for Projectors
I OUT2
PO
START
PO
STOP
PRBS Oscillator
The PRBS oscillator creates clock f PRBS1 , which can be
input to the PRBS generator. The oscillator frequency
is determined by the PRBS_N bit setting as shown in
Table 5. The recommended range for f PRBS1 is 100MHz
to 150MHz. Note that the PRBS oscillator is not phase-
SUBPIXEL
1 . . . . . . . . . m 1 . . . . . . . . . m
locked to the pixel clock. Therefore, OUT4 updates are
not synchronous to the pixel clock when the PRBS oscil-
PO
VIDEO2
1
PIXEL 1
1
PIXEL 2
lator is used.
PRBS Generator
Output 4 can be used to generate random noise. A
Figure 13. PO Subpixels
Table 4 . PO Subpixel Programming
TIME
32-bit shift register with feedback generates pseudo-
random codes. The PRBS_SEL bit selects the PRBS
clock source.
Serial Port and Registers
The serial port provides a 3-wire interface with bidirec-
t PIXEL
(ns)
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PO_M
1
1
1
2
2
2
2
3
4
4
4
4
5
5
6
6
PRBS_N
3
2
0
3
2
1
0
2
3
3
2
1
3
2
3
3
SUBPIXELS
(m)
16
16
16
24
24
24
24
32
40
40
40
40
48
48
56
56
f PRBS1
(MHz)
136
125
129
128
125
120
123
125
131
121
125
125
120
125
125
119
tional data (SDA), clock input (SCL), and a chip-select
input ( CS ) as shown in Figure 14. Table 6 shows the
register addresses. The external master initiates a data
transfer by asserting the CS pin.
Write Mode (R/ W = 0): The master generates 16 clock
cycles. It outputs 16 bits (MSB first) to the SDA line at the
falling edge of the clock. The master ends the transmis-
sion by setting CS high. The laser driver updates control
registers on the rising clock edge of the last data bit.
Read Mode (R/ W = 1): The master generates 16 clock
cycles. It outputs 8 bits (MSB first) to the SDA line at the
falling edge of the clock. The SDA line is released after
the R/ W bit has been transmitted. The slave outputs 8
bits of data (MSB first) at the rising edge of the clock. The
master ends the transmission by setting the CS pin high.
Read clock speed is determined by the external pullup
resistor and parasitic capacitance at the SDA pin.
Table 5. PRBS Oscillator
PRBS_N
0
1
2
3
f PRBS1 /f PO
0.9
0.8
0.75
0.68
15
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