参数资料
型号: MAX3634ETM+T
厂商: Maxim Integrated Products
文件页数: 5/8页
文件大小: 0K
描述: IC CLOCK PHASE ALIGNER 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 时钟相位定位器
PLL:
主要目的: GPON 光纤线路终端(OLT)接收器
输入: LVPECL
输出: LVPECL
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 是/是
频率 - 最大: 155.52MHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(7x7)
包装: 带卷 (TR)
General Description
Theory of Operation
The MAX3634 CPA provides serial clock and data out-
puts for GPON upstream bursts.
The burst-mode CPA operates on the principle that the
recovered clock from the ONT CDR is used at each
ONT to clock upstream data bursts out of the ONT con-
troller. The burst-mode CPA has logic that determines
the correct phase relationship between the upstream
data and the OLT reference clock at the beginning of
each ONT’s burst, and resamples the upstream data at
each bit using that clock.
The burst-mode CPA contains a phase-locked loop
(PLL) that synchronizes its oscillator to the reference
clock input. This oscillator drives a phase splitter, which
generates eight evenly spaced phases of the serial
clock, which are used to sample the input data at 1/8th
bit intervals in eight flip-flops. Combinatorial and
sequential logic measures the preamble, and based on
the phase of the preamble, determines which one of
the eight clock phases is at the center of the input data
bits. The data from the flip-flop associated with this
phase is then steered through a multiplexer to the CPA
output, which requires four or five additional clock peri-
ods until valid data is output. The CPA serial output
clock is continuous, without any phase jumps or dis-
continuities from burst to burst.
The burst-mode CPA requires a preamble sequence of
1010101010101 (13 bits) for correct phase alignment.
Typically, output begins after the 12th bit, although for
certain data/phase relationships, 13 bits are required.
An LVPECL-compatible lock status output is provided,
which indicates when the correct phase has been
acquired and valid serial output data is available. This
output remains low until reset by the burst reset input
(RST). The output data is disabled (held low) during the
period between reset and lock.
Reference Clock Input
The MAX3634 includes a PLL, which multiplies the ref-
erence clock by eight for use in the retiming circuitry.
For correct operation, the REFCLK input must be con-
nected to the OLT byte-rate reference clock, which
must be equal to 1/8th the serial data rate, and must
have a 40% to 60% duty cycle. This must be the same
clock source used to time the downstream data, and
the upstream data must be frequency locked to this
source.
The RATESEL input is used to configure 622Mbps or
1244Mbps operation; when RATESEL is high, the
MAX3634 operates at 622Mbps.
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
_______________________________________________________________________________________
5
MAX3634
LVPECL
REFCLK+
REFCLK-
LVPECL
SDI+
SDI-
TTL
RATESEL
622Mbps/1244Mbps
PLL/PHASE SPLITTER
DQ
MUX
SYNCHRONIZER
PHASE-ACQUISITION LOGIC
RST+
RST-
SDO+
SDO-
LVPECL
SCLK+
SCLK-
LVPECL
LOCK+
LOCK-
BURST-MODE CPA
φ0
φ7
Figure 2. Functional Block Diagram
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