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参数资料
| 型号： | MAX3676EHJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK RECOVERY 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（5x5） |
| 包装： | 带卷 (TR) |
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
6
_______________________________________________________________________________________
Pin Description
32
CFILT
RSSI Filter Capacitor Input. Connect a 47nF capacitor between CFILT and VCC.
30
ADI+
Positive Analog Data Input, 622.08Mbps serial-data stream
29
ADI-
Negative Analog Data Input, 622.08Mbps serial-data stream
28
INSEL
Input Select. Connect to GND to select digital data inputs or VCC for analog data inputs.
27
DDI-
Negative Digital Data Input, PECL, 622.08Mbps serial-data stream
26
DDI+
Positive Digital Data Input, PECL, 622.08Mbps serial-data stream
23
FIL+
Positive Filter Input. PLL loop filter connection. Internally connected to VCC.
22
FIL-
Negative Filter Input. PLL loop filter connection. Connect a 2.2μF capacitor between FIL- and FIL+.
20
PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used.
19
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used.
NAME
FUNCTION
1
OLC+
Positive Offset-Correction Loop Capacitor Input
2
OLC-
Negative Offset-Correction Loop Capacitor Input
PIN
3
RSSI
Received-Signal-Strength Indicator Output
4, 8, 16,
24, 25
GND
Supply Ground
9, 12, 15,
18, 21, 31
VCC
Positive Supply Voltage
7
LOP
Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal
is below threshold set by VTH.
6
VTH
Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCC if LOP function
is not used.
5
INV
Op Amp Inverting Input. Attach to ground if op amp is not used.
17
LOL
Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see the
Design Procedure section).
14
SDO+
Positive Serial-Data Output, PECL, 622.08Mbps
13
SDO-
Negative Serial-Data Output, PECL, 622.08Mbps
11
SCLKO+
Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+.
10
SCLKO-
Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-.
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相关代理商/技术参数 |
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| MAX3677CTJ+ | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN |
| MAX3677CTJ+T | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel |
| MAX3677EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3677 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3677 |
| MAX3678EVKIT+ | 功能描述:时钟和定时器开发工具 Not Available From Mouser RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| MAX3678UTN+ | 功能描述:时钟发生器及支持产品 Low-Jitter Frequency Synthesizer RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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