参数资料
型号: MAX3798ETJ+T
厂商: Maxim Integrated Products
文件页数: 5/35页
文件大小: 0K
描述: IC LIMITING AMP/VCSEL DVR 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
放大器类型: 限制
电路数: 1
输出类型: 差分
电流 - 电源: 97mA
电压 - 电源,单路/双路(±): 2.85 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
______________________________________________________________________________________
13
Pin Description
PIN
NAME
FUNCTION
1
LOS
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
2
MSEL
Mode-Select Input, TTL/CMOS. Set the MSEL pin or MODE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting MSEL and MODE_SEL logic-low for high-gain mode.
The MSEL pin is internally pulled down by a 75k
resistor to ground.
3, 6, 27, 30
VCCR
Power Supply. Provides supply voltage to the receiver block.
4
ROUT+
Noninverted Receive Data Output, CML. Back-terminated for 50
load.
5
ROUT-
Inverted Receive Data Output, CML. Back-terminated for 50
load.
7
VCCD
Power Supply. Provides supply voltage for the digital block.
8
DISABLE
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k
resistor to VCCT.
9
SCL
Serial Clock Input, TTL/CMOS. This pin has a 75k
internal pulldown.
10
SDA
Serial Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k
internal pullup,
but it requires an external 4.7k
pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
11
CSEL
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k
resistor to
ground.
12, 15, 18,
21
VCCT
Power Supply. Provides supply voltage to the transmitter block.
13
TIN+
Noninverted Transmit Data Input, CML
Typical Operating Characteristics—VCSEL Driver (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTING
MAX3798
toc35
SET_PWCTRL[3:0]
DETERMINISTIC
JITTER
(ps)
5
3
-5
-3
-1
1
3
4
5
6
7
8
9
10
2
-7
7
PATTERN = PRBS, DATA RATE = 10.32Gbps
EYE CROSSING
DOWN
UP
BIAS MONITOR CURRENT
vs. TEMPERATURE
MAX3798
toc36
TEMPERATURE (
°C)
MONITOR
CURRENT
A)
80
65
-25 -10
5
35
20
50
100
200
300
400
500
600
700
800
0
-40
95
IBIAS = 12mA
IBIAS = 8mA
IBIAS = 2mA
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