参数资料
型号: MAX3863ETJ+
厂商: Maxim Integrated
文件页数: 3/15页
文件大小: 0K
描述: IC LASR DRVR 2.7GBPS 3.6V 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管驱动器(光纤)
数据速率: 2.7Gbps
通道数: 1
电源电压: 3.15 V ~ 3.6 V
电流 - 电源: 58mA
电流 - 调制: 80mA
电流 - 偏置: 100mA
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
安装类型: 表面贴装
2.7Gbps Laser Driver with Modulation
Compensation
ELECTRICAL CHARACTERISTICS (continued)
(V CC = +3.15V to +3.6V, T A = -40°C to +85°C. Typical values are at V CC = +3.3V, I BIAS = 50mA, I MOD = 40mA, T A = +25°C, unless
otherwise noted.) (Notes 1, 9)
PARAMETER
Single-Ended Input (DC-Coupled)
SYMBOL
V IS
At high
At low
CONDITIONS
MIN
V CC - 1.0
TYP
V CC
MAX
V CC - 0.1
UNITS
V
At high
V CC +
0.05
V CC +
0.4
Single-Ended Input (AC-Coupled)
Differential Input Swing
Input Data Rate
Input Return Loss
Turn-Off Delay from EN
Setup Time
Hold Time
Pulse-Width Adjustment Range
V IS
V ID
RL IN
t SU
t HD
At low
DC-coupled
AC-coupled
NRZ (Note 3)
(Notes 3, 5)
EN = high (Note 3)
Figure 2 (Note 3)
Figure 2 (Note 3)
Z L = 25 Ω (Notes 3, 6)
f ≤ 2.7GHz
2.7GHz < f ≤ 4GHz
V CC -
0.4
0.2
0.2
90
90
± 185
3.2
17
14
± 220
V CC -
0.05
2.0
1.6
1.0
V
V P-P
Gbps
dB
μs
ps
ps
ps
Pulse-Width Stability
PWC+ and PWC- open (Notes 3, 6)
± 18.5
ps
Differential Pulse-Width Control
Input Range
Differential Mark Density
Differential Mark-Density Voltage
to Mark-Density Ratio
For PWC+ and PWC- (Notes 3, 7), V CM = 0.5V
0% to 100%, V MK + - V MK -
-1.0
15.5
1.0
± 0.85
V
V
V/%
Output Edge Speed
Output Overshoot
Random Jitter
Deterministic Jitter
t R , t F
δ
Z L = 25 Ω (20% to 80%) (Notes 3, 6)
Z L = 25 Ω (Note 3)
(Notes 3, 6)
Data Rate = 2.7Gbps (Notes 3, 8)
Data Rate = 3.2Gbps (Notes 3, 8)
50
± 7
0.8
8
10
85
1.3
40
40
ps
%
ps RMS
ps P-P
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Specifications at -40°C are guaranteed by design and characterization.
Excluding I BIAS , I MOD , I BIASMON , I MODMON , I FAIL , and I PWC . Input clock and data are AC-coupled.
Guaranteed by design and characterization.
An external capacitor at APCFILT1 and APCFILT2 is used to set the time constant.
For both data inputs DATA+, DATA- and clock inputs CLK+, CLK-.
Measured using a 2.7Gbps repeating 0000 0000 1111 1111 pattern.
For pulse width, PW = 100%: Rp = Rn = 500 Ω (or open) or PWC+ = PWC- ≈ +0.5V. For PW > 100%: Rp > Rn or PWC+ >
PWC-. For PW < 100%: Rp < Rn or PWC+ < PWC-.
Note 8: Measured using a 2 13 - 1 PRBS with 80 zeros + 80 ones input data pattern or equivalent.
Note 9: AC characterization performed using the circuit in Figure 1.
Note 10: Power-Supply Noise Rejection (PSNR) = 20log 10 (V NOISE (on VCC) / Δ V OUT ). V OUT is the voltage across the 25 Ω load when no
input is applied.
_______________________________________________________________________________________
3
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