- 您现在的位置：买卖IC网 > PDF目录1940 > MAX3880ECB+TD (Maxim Integrated Products)IC 1:16 DESERIALIZER 64-TQFP PDF资料下载
参数资料
| 型号： | MAX3880ECB+TD |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC 1:16 DESERIALIZER 64-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 750 |
| 功能： | 解串器 |
| 数据速率： | 2.5Gbps |
| 输入类型： | 串行 |
| 输出类型： | LVDS |
| 输入数： | 1 |
| 输出数： | 16 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________
5
NAME
FUNCTION
1, 17, 25, 33,
41, 49, 56,
62, 64
GND
Ground
PIN
Pin Description
2
FIL+
Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
3
FIL-
Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
4, 7, 10, 13,
24, 32, 40,
48, 57
VCC
+3.3V Supply Voltage
5
PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
6
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
8
SDI+
Positive Serial Data Input. 2.488Gbps data stream.
9
SDI-
Negative Serial Data Input. 2.488Gbps data stream.
11
SLBI+
Positive System Loopback Input. 2.488Gbps data stream.
12
SLBI-
Negative System Loopback Input. 2.488Gbps data stream.
14
SIS
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
15
SYNC-
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
16
SYNC+
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
18
PCLK-
Negative Parallel Clock LVDS Output
19
PCLK+
Positive Parallel Clock LVDS Output
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
PD0- to
PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0+ to
PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
63
LOL
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k
pull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
EP
Exposed Pad
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
相关PDF资料 |
PDF描述 |
|---|---|
| MAX3885ECB+TD | IC 1:16 DESERIALIZER 64-TQFP |
| MAX388CWG | IC MULTIPLEXER 8X1 24SOIC |
| MAX3890ECB+TD | IC 16:1 SERIALIZER 64-TQFP-EP |
| MAX3892ETH+T | IC 4:1 SERIALIZER SONET 44-TQFN |
| MAX392ESE | IC SWITCH QUAD SPST 16SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3881ECB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3881ECB+D | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3881ECB+TD | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3881ECB-D | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3881ECB-TD | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
发布紧急采购，3分钟左右您将得到回复。