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| 型号： | MAX3892ETH+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/11页 |
| 文件大小： | 0K |
| 描述： | IC 4:1 SERIALIZER SONET 44-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 串行器 |
| 数据速率： | 2.7Gbps |
| 输入类型： | LVDS |
| 输出类型： | CML |
| 输入数： | 4 |
| 输出数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-WFQFN 裸露焊盘 |
| 供应商设备封装： | 44-TQFN-EP（7x7） |
| 包装： | 带卷 (TR) |
MAX3892
latching high FIFOERROR. To clear this condition,
RESET must be asserted high for at least 4UI. FIFOER-
ROR may be tied directly to the RESET input to recen-
ter the FIFO. After reset, the full elastic range of the
FIFO is available again.
Frequency Synthesizer
The PLL synthesizes a 2.5Gbps/2.7Gbps clock (SCLKO) from
an external reference clock. The PLL reference clock (RCLK)
may be 622.08MHz/666.53MHz, 155.52MHz/166.6MHz,
77.76MHz/83.3MHz or 38.88MHz/41.65MHz as determined
by CLKSET and RATESET. See Table 2 for the reference fre-
quency selection. The parallel output clock PCLKO is also
derived from the synthesizer to be SCLKO divided by 4. A
TTL-compatible loss-of-lock indicator, LOL, goes low when the
VCO is unable to lock to the reference frequency. Frequency
difference on RCLK with respect to the divided down SCLKO
greater than 500ppm is indicated by a low state on LOL.
When the frequency difference between the clocks is less
than 250ppm, LOL high indicates a lock condition.
System Loopback
The MAX3892 is designed to allow system loop-back
testing. The loop-back outputs (SLBO+, SLBO-) of the
MAX3892 may be directly connected to the loop-back
inputs of a deserializer (such as the MAX3882) for sys-
tem diagnostics. Alternatively, the SLBO pins can be
programmed to provide a 622MHz reference clock.
This reference clock can provide a clock hold-over sig-
nal to a clock and data recovery (CDR) circuit in the
event of loss of signal (LOS).
Design Procedure
Clock Mode Selection
The frequencies of the MAX3892 can be set up using
CLKSET, RATESET, and MODE as shown in Tables 2
and 3.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3892 clock and data inputs and
outputs.
Exposed-Pad Package
The EP 44-pin QFN incorporates features that provide a
very low thermal-resistance path for heat removal from
the IC to a PC board. The MAX3892’s EP must be sol-
dered directly to a ground plane with good thermal
conductance.
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
8
_______________________________________________________________________________________
SLBPD
SLBEN
SLBO
± OUTPUT
VIL
X
Power-Down SLBO Output
VIH
VIL
622MHz/667MHz Clock
Output
VIH
2.5Gbps/2.7Gbps System
Loop-Back Output
Table 1. Loop-Back Operation Mode
CLKSET
RATESET
RCLK
± FREQUENCY (MHz)
VCC
666
VCC
GND
622
VCC
166.5
OPEN
GND
155.52
VCC
83.25
30k
Ω to GND
GND
77.76
VCC
41.63
GND
38.88
Table 2. Setting the Reference Clock
Frequency
MODE
RATESET
PCLKI
±
FREQUENCY
(MHz)
SCLKO
±
FREQUENCY
(GHz)
VCC
666Hz
2.666
VCC
GND
622Hz
2.488
VCC
666Hz
Disabled
OPEN
GND
622Hz
Disabled
VCC
333Hz
Disabled
30k
Ω
to
GND
311Hz
Disabled
VCC
333Hz
2.666
GND
311Hz
2.488
Table 3. Setting the Clock Mode
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| MAX389CPN | 功能描述:多路器开关 IC RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
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| MAX389CWG | 功能描述:多路器开关 IC RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
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