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参数资料
| 型号： | MAX3946ETG+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 16/29页 |
| 文件大小： | 0K |
| 描述： | IC LASER DVR SFP 11.3GBPS 24TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 75 |
| 类型： | 激光二极管驱动器 |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 2.85 V ~ 3.63 V |
| 电流 - 电源： | 68mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 80mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
3-Wire Interface
The device implements a proprietary 3-wire digital inter-
face. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to a logic-high. All data transfers are most significant bit
(MSB) first.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
device. The RWN bit determines if the cycle is read or
write. See Table 3.
Register Addresses
The device contains 13 registers available for program-
ming. Table 4 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
line at the falling edge of the clock. The master closes
the transmission by setting CSEL to 0. Figure 5 shows
Read Mode (RWN = 1)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at the falling edge of the clock. The SDA line is released
after the RWN bit has been transmitted. The slave out-
puts 8 bits of data (MSB first) at the rising edge of the
clock. The master closes the transmission by setting
CSEL to 0. Figure 5 shows the interface timing.
Mode Control
Normal mode allows read-only instruction for all regis-
ters except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal mode.
Doing so speeds up the laser control update through the
3-wire interface by a factor of two. The normal mode is
the default mode.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2)
registers. To enter the setup mode, the MODECTRL
register (address = H0x0E) must be set to H0x12. After
the MODECTRL register has been set to H0x12, the
next operation is unrestricted. The setup mode is auto-
matically exited after the next operation is finished. This
sequence must be repeated if further unrestricted set-
tings are necessary.
the interface timing.
Table 3. Digital Communication Word Structure
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Address
RWN
Data that is written or read
Table 4. Register Descriptions and Addresses
ADDRESS
H0x05
H0x06
H0x07
H0x08
H0x09
H0x0A
H0x0B
H0x0C
H0x0D
H0x0E
H0x0F
H0x10
H0x11
NAME
TXCTRL
TXSTAT1
TXSTAT2
SET_IBIAS
SET_IMOD
IMODMAX
IBIASMAX
MODINC
BIASINC
MODECTRL
SET_PWCTRL
SET_TXDE
SET_TXEQ
FUNCTION
Transmitter Control Register
Transmitter Status Register 1
Transmitter Status Register 2
Bias Current Setting Register
Modulation Current Setting Register
Maximum Modulation Current Setting Register
Maximum Bias Current Setting Register
Modulation Current Increment Setting Register
Bias Current Increment Setting Register
Mode Control Register
Pulse-Width Control Register
Deemphasis Control Register
Equalization Control Register
16
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