参数资料
型号: MAX3946ETG+
厂商: Maxim Integrated
文件页数: 20/29页
文件大小: 0K
描述: IC LASER DVR SFP 11.3GBPS 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 75
类型: 激光二极管驱动器
数据速率: 11.3Gbps
通道数: 1
电源电压: 2.85 V ~ 3.63 V
电流 - 电源: 68mA
电流 - 调制: 80mA
电流 - 偏置: 80mA
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 托盘
安装类型: 表面贴装
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Bias Current Increment Setting Register (BIASINC)
Bit #
Name
Default Value
7
SET_IBIAS
[0] (LSB)
0
6
X
0
5
X
0
4
BIASINC
[4] (MSB)
0
3
BIASINC
[3]
0
2
BIASINC
[2]
0
1
BIASINC
[1]
0
0
BIASINC
[0] (LSB)
0
ADDRESS
H0x0D
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0].
Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the
SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two’s complement string.
Mode Control Register (MODECTRL)
Bit #
Name
Default Value
7
MODECTRL
[7] (MSB)
0
6
MODECTRL
[6]
0
5
MODECTRL
[5]
0
4
MODECTRL
[4]
0
3
MODECTRL
[3]
0
2
MODECTRL
[2]
0
1
MODECTRL
[1]
0
0
MODECTRL
[0] (LSB)
0
ADDRESS
H0x0E
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables the user to switch between normal and setup modes.
The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write opera-
tion. Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Pulse-Width Control Register (SET_PWCTRL)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
X
X
SET_PWCTRL SET_PWCTRL SET_PWCTRL SET_PWCTRL
[3] (MSB) [2] [1] [0] (LSB)
H0x0F
Default Value
X
X
X
X
0
0
0
0
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
Deemphasis Control Register (SET_TXDE)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE
[5] (MSB) [4] [3] [2] [1] [0] (LSB)
H0x10
Default Value
X
X
0
0
0
0
0
1
Bits 5 to 0: SET_TXDE[5:0]. This is a 6-bit register used to control the amount of deemphasis on the transmitter output.
When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis
is set as a percentage of modulation current.
Equalization Control Register (SET_TXEQ)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
X
X
X
SET_TXEQ SET_TXEQ
[2] [1]
X
H0x11
Default Value
X
X
X
X
X
0
0
X
Bits 2 to 1: SET_TXEQ[2:1]. These 2 bits are used to control the amount of equalization on the transmitter input. See
Table 1 for more information.
20
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