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| 型号： | MAX3964AETP+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC AMP LIMITING SGNL DET 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 75 |
| 类型： | 限幅放大器 |
| 应用： | 光纤学网络 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-TQFN-EP（4x4） |
| 包装： | 管件 |
MAX3964A/MAX3968
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
6
_______________________________________________________________________________________
Detailed Description
The MAX3964A contains a series of limiting amplifiers
and power detectors, offset correction, data-squelch cir-
cuitry, and PECL output buffers for data and loss-of-sig-
nal (LOS) outputs. The MAX3968 provides PECL LOS
outputs with data outputs suitable for 266Mbps. Figure 1
shows a functional diagram of the MAX3964A/MAX3968.
Limiting Amplifiers
A series of four limiting amplifiers provides gain of
approximately 65dB.
Power Detector
Each amplifier stage contains a full-wave logarithmic
detector (FWD), which indicates the RMS input signal
power. The FWD outputs are summed together at the
FILTER pin where the signal is filtered by an external
capacitor (CFILTER) connected between FILTER and
VCC. The FILTER signal generates the RSSI output volt-
age, which is proportional to the input power in deci-
bels. When LOS+ is low, VRSSI is approximated by the
following equation:
VRSSI (V) = 1.2V + 0.5log (VIN)
where VIN is measured in mVP-P.
This relation translates to a 25mV increase in VRSSI for
every 1dB increase in VIN (25mV/dB). The RSSI output is
reduced approximately 120mV when LOS+ is asserted.
PECL Outputs
The data outputs (OUT+, OUT-) and the MAX3964A/
MAX3968 loss-of-signal outputs (LOS+, LOS-) are sup-
ply-referenced PECL outputs. Standard PECL termina-
tion at each output of 50 to (VCC - 2V) is recommended
for best performance.
Input Offset Correction
A low-frequency feedback loop around the limiting
amplifier improves receiver sensitivity and powerdetec-
tor accuracy. The offset-correction loop’s bandwidth is
determined by an external capacitor (CAZ) connected
between the CZP and CZN pins.
The offset correction is optimized for data streams with
a 50% duty cycle. A different average duty cycle
results in increased pulse-width distortion and loss of
sensitivity. The offset-correction circuitry is less sensi-
tive to variations of input duty cycle (for example, the
40% to 60% duty cycle encountered in 4B/5B coding)
when the input is less than 30mVP-P.
CZN
CZP
OUT+/OUT-
LOS+/LOS-
RSSI
SQUELCH
LOS+
LOS
COMPARATOR
FILTER
IN+/IN-
VCC
VCCO
R1
R2
VTR
SUB
GND
INV
VCC
CFILTER
FWD = FULL-WAVE DETECTOR
CAZ
LIMITER
OFFSET
CORRECTION
LIMITER
I
O
LIMITER
FWD
1.2V
REFERENCE
MAX3964A
MAX3968
Figure 1. Functional Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3964AETP+ | 功能描述:限幅放大器 3-5.5V 125-266Mbps Limiting Amp RoHS:否 制造商:Micrel 输入电压范围（最大值）:3.6 V 工作电源电压:3.3 V 电源电流:40 mA 工作温度范围:- 40 C to + 85 C 封装 / 箱体:MSOP-10 封装:Tube |
| MAX3964AETP+T | 功能描述:限幅放大器 3-5.5V 125-266Mbps Limiting Amp RoHS:否 制造商:Micrel 输入电压范围（最大值）:3.6 V 工作电源电压:3.3 V 电源电流:40 mA 工作温度范围:- 40 C to + 85 C 封装 / 箱体:MSOP-10 封装:Tube |
| MAX3964AETP-T | 功能描述:限幅放大器 3-5.5V 125-266Mbps Limiting Amp RoHS:否 制造商:Micrel 输入电压范围（最大值）:3.6 V 工作电源电压:3.3 V 电源电流:40 mA 工作温度范围:- 40 C to + 85 C 封装 / 箱体:MSOP-10 封装:Tube |
| MAX3964C/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3964CEP | 制造商:Maxim Integrated Products 功能描述:+3.0V TO +5.5V, 125MBPS TO 266MBPS LINITING A - Bulk |
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