参数资料
型号: MAX3982UTE+T
厂商: Maxim Integrated Products
文件页数: 2/15页
文件大小: 0K
描述: IC DRIVER SFP CABLE 16-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 驱动器
驱动器/接收器数: 1/0
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-TQFN-EP(3x3)
包装: 带卷 (TR)
MAX3982
SFP Copper-Cable Preemphasis Driver
10
______________________________________________________________________________________
PIN
NAME
FUNCTION
1VCC1
Power-Supply Connection for Input. Connect to +3.3V.
2
IN+
Positive Data Input, CML. This input is internally terminated with 50
Ω to VCC1.
3
IN-
Negative Data Input, CML. This input is internally terminated with 50
Ω to VCC1.
4, 8, 9
GND
Circuit Ground
5
OUTLEV
Output-Swing Control Input, LVTTL with 40k
Ω Internal Pullup. Set to TTL high or open for maximum
output swing, or set to TTL low for reduced swing.
6
PE1
Output Preemphasis Control Input, LVTTL with 10k
Ω Internal Pullup. This pin is the most significant bit
of the 2-bit preemphasis control. Set high or open to assert this bit.
7
PE0
Output Preemphasis Control Input, LVTTL with 10k
Ω Internal Pullup. This pin is the least significant bit
of the 2-bit preemphasis control. Set high or open to assert this bit.
10
OUT-
Negative Data Output, CML. This output is terminated with 50
Ω to VCC2.
11
OUT+
Positive Data Output, CML. This output is terminated with 50
Ω to VCC2.
12, 13
VCC2
Power-Supply Connection for Output. Connect to +3.3V.
14
TX_DISABLE
Transmitter Disable Input, LVTTL with 10k
Ω Internal Pullup. When high or open, differential output is
40mVP-P. Set low for normal operation.
15
LOS
Loss-of-Signal Detect, TTL Output. This output is open-collector TTL, and therefore requires an external
4.7k
Ω to 10kΩ pullup resistor (5.5V maximum). This output sinks current when the input signal level is
valid.
16
LOSLEV
LOS Sensitivity Control Input, LVTTL with 40k
Ω Internal Pullup. Set to TTL high or open for less
sensitivity (higher assert threshold). Set to TTL low for more sensitivity (lower assert threshold).
EP
EXPOSED
PAD
Exposed Pad. For optimal thermal conductivity, this pad must be soldered to the circuit board ground.
Pin Description
VCC1
1
IN+
2
IN-
3
GND
4
VCC2
12
OUT+
11
OUT-
10
GND
9
OUTLEV
5
PE1
6
PE0
7
GND
8
LOSLEV
16
LOS
15
TX_DISABLE
14
V
CC2
13
MAX3982UTE
EXPOSED PAD*
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND
FOR PROPER THERMAL OPERATION OF THE MAX3982.
TOP VIEW
THIN QFN
Pin Configuration
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