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参数资料
| 型号： | MAX3982UTE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER SFP CABLE 16-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 驱动器 |
| 驱动器/接收器数： | 1/0 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 供应商设备封装： | 16-TQFN-EP（3x3） |
| 包装： | 带卷 (TR) |
MAX3982
SFP Copper-Cable Preemphasis Driver
_______________________________________________________________________________________
3
Note 1: Guaranteed by design and characterization.
Note 2: PE1 = PE0 = 1 for maximum preemphasis, load is 50
Ω ±1% at each side, and the pattern is 0000011111 at 1Gbps.
Note 3: Measured at point B in Figure 2 using 0000011111 at 1Gbps. PE1 = PE0 = 0 for minimum preemphasis. For transition time,
the 0% reference level is the steady-state level after four zeros, just before the transition. The 100% reference level is the
maximum voltage of the transition.
Note 4: Tested with CJTPAT, as well as this pattern: 19 zeros, 1, 10 zeros, 1010101010 (D21.5 character), 1100000101 (K28.5+
character), 19 ones, 0, 10 ones, 0101010101 (D10.2 character), 0011111010 (K28.5 character).
Note 5: Cables are unequalized, Amphenol Spectra-Strip 24AWG. Residual deterministic jitter is the difference between the source
jitter at point A, and load jitter at point D in Figure 2. The deterministic jitter at the output of the transmission line must be
from media-induced loss and not from clock-source modulation.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at TA = +25°C and VCC = +3.3V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EQUALIZER AND CABLE DRIVER SPECIFICATIONS
Input Swing
Measured differentially at point A of Figure
2 (Note 1)
600
2000
mVP-P
Input Resistance
Measured differentially
85
100
115
Ω
Input Return Loss
100MHz to 2GHz (Note 1)
10
dB
TX_DISABLE = low,
OUTLEV = high
1450
1800
TX_DISABLE = low,
OUTLEV = low
1000
1350
Differential Output Swing
Measured
differentially at point
B of Figure 2
(Notes 1, 2)
TX_DISABLE = high
40
mVP-P
Common-Mode Output
(OUT+) + (OUT-), measured at point B of
Figure 2; TX_DISABLE = low, OUTLEV =
high (Notes 1, 2)
60
mVP-P
Output Resistance
OUT+ or OUT- to VCC, single ended
42
50
58
Ω
Output Return Loss
100MHz to 2GHz (Note 1)
10
dB
Output Transition Time
tr, tf
20% to 80% (Notes 1, 3)
50
80
ps
Random Jitter
(Notes 1, 3)
1.6
psRMS
PE1
PE0
00
2
01
4
10
8
Output Preemphasis
See Figure 1
11
14
dB
Source to IN
OUT to Load
PE1
PE0
1m, 24AWG
0
5m, 24AWG
0
1
10m, 24AWG
1
0
Residual Output Deterministic
Jitter at 1.0625Gbps to
2.125Gbps (Notes 1, 4, 5)
6 mil
FR4
≤ 10in
15m, 24AWG
1
0.10
0.15
UIP-P
Source to IN
OUT to Load
PE1
PE0
1m, 24AWG
0
5m, 24AWG
0
1
10m, 24AWG
1
0
Residual Output Deterministic
Jitter at 4.25Gbps (Notes 1, 4, 5)
6 mil
FR4
≤ 10in
15m, 24AWG
1
0.15
0.20
UIP-P
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