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参数资料
| 型号： | MAX3992UTG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC DATA RECOVERY W/EQ 24-TQFN |
| 标准包装： | 2,500 |
| 类型： | 时钟和数据恢复（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH.XFP 光学接收器 |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 693.5MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +4.0V
Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V)
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V)
Continuous Power Dissipation (TA = +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C) .........1355mW
Junction Temperature Range .............................-40°C to+150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s) ..……………………..+300°C
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
ICC
108
145
mA
DATA INPUT SPECIFICATION (SDI±)
Single-Ended Input Resistance
RSE
42
50
58
Differential Input Resistance
RD
84
100
116
Single-Ended Input Resistance
Matching
±5
%
0.1GHz to 5.5GHz (Note 1)
15
Differential-Input Return Loss
SDD11
5.5GHz to 12GHz (Note 1)
6
dB
Differential to Common-Mode
Conversion
SCD11
0.1GHz to 15GHz
17
dB
Common-Mode Input Return
Loss
SCC11
0.1GHz to 15GHz
7
dB
REFERENCE CLOCK SPECIFICATION (REFCLK±)
Single-Ended Input Resisitance
84
100
116
Differential Input Resistance
168
200
232
CML OUTPUT SPECIFICATION (SDO±)
SDO± Differential Output Swing
(Note 2)
575
650
725
mVP-P
SDO± Output Common-Mode
Voltage
RL = 50 to VCC
VCC -
0.16
V
SCLKO± Differential Output
380
mVP-P
Single-Ended Output Resistance
42
50
58
Differential Output Resistance
RO
84
100
116
Single-Ended Output Resistance
Matching
±5
%
0.1GHz to 5.5GHz (Note 1)
13
Differential-Output Return Loss
SDD22
5.5GHz to 12GHz (Note 1)
8
dB
Rise/Fall Time
(20% to 80%) (Note 2)
18
23
30
ps
Power-Down Assert Time
(Note 3)
50
s
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