参数资料
型号: MAX4294EUD+T
厂商: Maxim Integrated Products
文件页数: 3/18页
文件大小: 0K
描述: IC OP AMP R-R I/O 14-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
放大器类型: 通用
电路数: 4
输出类型: 满摆幅
转换速率: 0.2 V/µs
增益带宽积: 500kHz
电流 - 输入偏压: 15nA
电压 - 输入偏移: 200µV
电流 - 电源: 100µA
电流 - 输出 / 通道: 20mA
电压 - 电源,单路/双路(±): 1.8 V ~ 5.5 V,±0.9 V ~ 2.75 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
within 100mV of VCC and is capable of driving a 485
load resistor to VEE:
The same application can drive a 220k
load resistor
when terminated in VCC/2 (0.9V in this case).
Driving Capacitive Loads
The MAX4291/MAX4292/MAX4294 are unity-gain stable
for loads up to 100pF (see the Load Resistor vs.
Capacitive Load graph in the Typical Operating
Characteristics). Applications that require greater
capacitive-drive capability should use an isolation
resistor between the output and the capacitive load
(Figure 7). Note that this alternative results in a loss of
gain accuracy because RISO forms a voltage divider
with the load resistor.
Power-Supply Bypassing and Layout
The MAX4291/MAX4292/MAX4294 family operates from
either a single 1.8V to 5.5V supply or dual ±0.9V to
±2.75V supplies. For single-supply operation, bypass
the power supply with a 100nF capacitor to VEE (in this
case GND). For dual-supply operation, both the VCC
and the VEE supplies should be bypassed to ground
with separate 100nF capacitors.
Good PC board layout techniques optimize perfor-
mance by decreasing the amount of stray capacitance
at the op amp’s inputs and output. To decrease stray
capacitance, minimize trace lengths and widths by
placing external components as close as possible to
the op amp. Surface-mount components are an excel-
lent choice.
Using the MAX4291/MAX4292/MAX4294
as Comparators
Although optimized for use as operational amplifiers,
the MAX4291/MAX4292/MAX4294 can also be used as
rail-to-rail I/O comparators. Typical propagation delay
depends on the input overdrive voltage, as shown in
Figure 8. External hysteresis can be used to minimize
the risk of output oscillation. The positive feedback cir-
cuit, shown in Figure 9, causes the input threshold to
change when the output voltage changes state. The
two thresholds create a hysteresis band that can be
calculated by the following equations:
R
(1.8V
0.1V)
3.5mA
485
to V
LEE
=
=
MAX4291/MAX4292/MAX4294
Ultra-Small, 1.8V, Power,
Rail-to-Rail I/O Op Amps
______________________________________________________________________________________
11
RISO
CL
RL
MAX4291
MAX4292
MAX4294
AV =
RL
≈ 1
RL + RISO
OUT
IN
Figure 7a. Using a Resistor to Isolate a Capacitive Load from
the Op Amp
OUT
IN
0
100mV
0
100mV
10
s/div
VCC = 2.4V, RL = 2k
TO VEE, CL = 1000pF
Figure 7b. Pulse Response Without Isolating Resistor
OUT
IN
0
100mV
0
100mV
10
s/div
VCC = 2.4V, RL = 2k
TO VEE, CL = 1000pF, RISO = 100
Figure 7c. Pulse Response with Isolating Resistor (100
)
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