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参数资料
| 型号： | MAX4807CTN+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC DGTL PULSER DUAL 56TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 通用型，过电压保护 |
| 电流 - 电源： | 100µA |
| 电源电压： | 2.7 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 供应商设备封装： | 56-TQFN-EP（7x7） |
| 包装： | 带卷 (TR) |
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
device. In this case, whenever both the INP_ and INN_
inputs are low and the INC_ input is high, the active clamp
circuit pulls the output to GND through the OCP_ and
OCN_ outputs (see Table 1 for more information).
Power-Supply Ramping and
Gate-Source Short Circuit
The MAX4806/MAX4807/MAX4808 include a gate-
source short circuit that is controlled by the enable input
(EN_). When SHDN is high and EN_ is low, a 60 Ω switch
shorts together the gate and source of the high-side out-
put FET. At the same time, a similar switch shorts the
gate and source of the low-side output FET (Table 1).
The gate-source short circuit prevents accidental turn-
on of the output FETs due to the ramping voltage on
V PP_ and V NN_ , and allows for faster ramping rates and
smaller delay times between pulsing modes.
Shutdown Mode
SHDN is common to both channel 1 and channel 2 and
powers up or down the device. Drive SHDN low to power
down all internal circuits (except the clamp circuits).
When SHDN is low, the device is in the lowest power
state (1μA) and the gate-source short circuit is disabled.
The device takes 36.8ns (typ) to become active when
SHDN is disabled.
Thermal Protection
A thermal-shutdown circuit with a typical threshold of
pation limit. See the Typical Operating Characteristics
section for more information on typical supply currents
versus switching frequencies.
The device consumes most of the supply current from
V CC_ supply to charge and discharge internal nodes
such as the gate capacitance of the high-side FET (C P )
and the low-side FET (C N ). Neglecting the small quies-
cent supply current and a small amount of current used
to charge and discharge the capacitances at the inter-
nal gate clamp FETs, the power consumption can be
estimated as follows:
? f f ? ? ?
P VCC_ = ? ( C N × V CC _ 2 × IN ) + ( C P × V CC _ 2 × IN ) ? × ( B R F × BTD )
f IN = f INN _ = f INP _
Where f INN_ and f INP_ are the switching frequency of
the inputs INN_ and INP_ respectively, and where BRF
is the Burst Repetition Frequency and BTD is the Burst
Time Duration. The typical value gate capacitances of
the power FET are C N = 0.3μF and C P = 0.6μF.
For an output load that has a resistance of R L and
capacitance of C L , the MAX4806/MAX4807/MAX4808
power dissipation can be estimated as follows (assume
square-wave output and neglect the resistance of the
switches):
?
(
P VPP_ = ? ? ? ( C O + C L ) × f IN × V PP _ ? V NN _
? ?
)
? V
+ ?
?? ? R L
1 ?
?
× ? × ( BRF × BTD ) ?
? ?
?
+155°C prevents damage due to excessive power dis-
sipation. When the junction temperature exceeds T J =
+150°C, all outputs are disabled. Normal operation typ-
ically resumes after the IC’s junction temperature drops
?
?
2 ? PP _
?
2
2 ?
?
below +130°C.
Applications Information
AC-Coupling Capacitor Selection
The value of all AC-coupling capacitors (between C DP_
and C GP_ , and between C DN_ and C GN_ ) should be
between 1nF to 10nF. The voltage rating of the capaci-
tor should be greater than V PP_ and V NN_ . The capaci-
tors should be placed as close as possible to the
device.
Because INP_ and part of INC_ are AC-coupled to the
output devices, they cannot be driven high indefinitely
when the device is active.
Power Dissipation
The power dissipation of the MAX4806/MAX4807/
MAX4808 consists of three major components caused
by the current consumption from V CC_ , V PP_ , and V NN_ .
The sum of these components (P VCC_ , P VPP_ , and
P VNN_ ) must be kept below the maximum power-dissi-
Where C O is the output capacitance of the device.
Power Supplies and Bypassing
The MAX4806/MAX4807/MAX4808 operate from inde-
pendent supply voltage sets (only V DD and V SS are
common to both channels). The logic input circuit oper-
ates from a +2.7V to +6V single supply (V DD ). The
level-shift driver dual supplies, V CC_ /V EE_ operate from
±4.75V to ±12.6V.
The V PP_ /V NN_ high-side and low-side supplies are dri-
ven from a single positive supply up to +220V, from a
single negative supply up to -200V, or from ±110V dual
supplies. Either V PP_ or V NN_ can be set at 0V. Bypass
each supply input to ground with a 0.1μF capacitor as
close as possible to the device.
Depending on the application, additional bypassing
may be needed to maintain the input of both V NN_ and
V PP_ stable during output transitions. For example, with
C OUT = 100pF and R OUT = 100 Ω load, the use of an
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX480C/D | 功能描述:运算放大器 - 运放 RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
| MAX480CPA | 功能描述:运算放大器 - 运放 RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
| MAX480CSA | 功能描述:运算放大器 - 运放 RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
| MAX480CSA+ | 功能描述:运算放大器 - 运放 RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
| MAX480CSA+T | 功能描述:运算放大器 - 运放 RoHS:否 制造商:STMicroelectronics 通道数量:4 共模抑制比（最小值）:63 dB 输入补偿电压:1 mV 输入偏流（最大值）:10 pA 工作电源电压:2.7 V to 5.5 V 安装风格:SMD/SMT 封装 / 箱体:QFN-16 转换速度:0.89 V/us 关闭:No 输出电流:55 mA 最大工作温度:+ 125 C 封装:Reel |
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