参数资料
型号: MAX4940BETN+
厂商: Maxim Integrated Products
文件页数: 8/18页
文件大小: 0K
描述: IC DGTL PULSER HI-VOLT 56TQFN
标准包装: 37
应用: 医疗用超声波成像,声纳
电源电压: 2.37 V ~ 6 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16, 27, 29,
34, 37, 42,
44, 55
17, 54
18
19
20
21
22
23
24
25
NAME
INP1A
CLP1A
INN1A
INP2A
CLP2A
INN2A
AGND
EN
INP2B
CLP2B
INN2B
INP1B
CLP1B
INN1B
V EE
GND
V CC
C DP1B
C DN1B
C DN2B
C DP2B
C GP2B
C GN2B
C GN1B
C GP1B
FUNCTION
Channel 1A High-Side Logic Input. See the Truth Tables section.
Channel 1A Clamp Logic Input. Clamp is turned on when CLP1A is high and when INP1A and
INN1A are low. See the Truth Table section.
Channel 1A Low-Side Logic Input. See the Truth Tables section.
Channel 2A High-Side Logic Input. See the Truth Tables section.
Channel 2A Clamp Logic Input. Clamp is turned on when CLP2A is high and when INP2A and
INN2A are low. See the Truth Tables section.
Channel 2A Low-Side Logic Input. See the Truth Tables section.
Analog Ground. Must be connected to common GND.
Enable Logic Input. Drive EN high to enable OUT1A, OUT1B, OUT2A, and OUT2B.
Channel 2B High-Side Logic Input. See the Truth Tables section.
Channel 2B Clamp Logic Input. Clamp is turned on when CLP2B is high and when INP2B and
INN2B are low. See the Truth Tables section.
Channel 2B Low-Side Logic Input. See the Truth Tables section.
Channel 1B High-Side Logic Input. See the Truth Tables section.
Channel 1B Clamp Logic Input. Clamp is turned on when CLP1B is high and when INP1B and
INN1B are low. See the Truth Tables section.
Channel 1B Low-Side Logic Input. See the Truth Tables section.
Negative Supply Input. Gate-drive supply voltage for the clamp. Bypass V EE to GND with a 0.1 F F
capacitor as close as possible to the device.
Ground
Gate-Drive Supply Voltage Input. Bypass V CC to GND with a 0.1 F F capacitor as close as possible
to the device.
Channel 1B High-Side Driver Output. Connect a 3.3nF capacitor between C DP1B and C GP1B as
close as possible to the device.
Channel 1B Low-Side Driver Output. Connect a 3.3nF capacitor between C DN1B and C GN1B as
close as possible to the device.
Channel 2B Low-Side Driver Output. Connect a 3.3nF capacitor between C DN2B and C GN2B as
close as possible to the device.
Channel 2B High-Side Driver Output. Connect a 3.3nF capacitor between C DP2B and C GP2B as
close as possible to the device.
Channel 2B High-Side Gate Input. Connect a 3.3nF capacitor between C DP2B and C GP2B as close
as possible to the device.
Channel 2B Low-Side Gate Input. Connect a 3.3nF capacitor between C DN2B and C GN2B as close
as possible to the device.
Channel 1B Low-Side Gate Input. Connect a 3.3nF capacitor between C DN1B and C GN1B as close
as possible to the device.
Channel 1B High-Side Gate Input. Connect a 3.3nF capacitor between C DP1B and C GP1B as close
as possible to the device.
8
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