参数资料
型号: MAX5051AUI+T
厂商: Maxim Integrated Products
文件页数: 10/21页
文件大小: 0K
描述: IC REG CTRLR PWM VM 28-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 500kHz
占空比: 48%
电源电压: 11 V ~ 76 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
Parallelable, Clamped Two-Switch
Power-Supply Controller IC
Pin Description (continued)
PIN
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
LXH
LXL
CS
DRVL
PGND
DRVDD
DRVB
XFRMRH
DRVH
BST
AVIN
GND
UVLO
STARTUP
FLTINT
SYNCIN
FUNCTION
Synchronous-Pulse Transformer Driver, PMOS Open Drain. LXH is the high-side driver for the secondary-
side synchronous-pulse transformer. LXH can also drive a high-speed switching optocoupler. If not
used, connect LXH to LXVDD.
Synchronous-Pulse Transformer Driver, NMOS Open Drain. LXL is the low-side driver for the secondary-
side synchronous-pulse transformer. LXL can also drive a high-speed switching optocoupler. If not used,
connect LXL to PGND.
Current-Sense Input. The current-limit threshold is internally set to 156mV relative to PGND. The device
has an internal noise filter. If necessary, connect an additional external RC filter.
Gate-Drive Output for Low-Side MOSFET. DRVL is capable of sourcing and sinking approximately 2A
peak current.
Power Ground
Supply Input for Low-Side MOSFET Driver. Bypass DRVDD locally with good quality 1μF || 0.1μF ceramic
capacitors. DRVDD is normally connected to REG9.
Gate-Drive Output for Boost MOSFET. Connect the gate of a small high-voltage external FET to this pin to
enable charging of the high-side boost capacitor connected between pins 20 and 22. This FET may be
necessary to keep the boost capacitor charged at light loads.
Transformer Input. Transformer primary high-side connection.
Gate-Drive Output for High-Side MOSFET
Boost Input. Boost supply connection point for the high-side MOSFET driver. Connect at least a 1μF ||
0.1μF ceramic capacitor from BST to XFRMRH with short and wide PC board traces. If the voltage across
the boost capacitor falls below the high-side undervoltage lockout threshold, the DRVH output stops
switching.
Supply Voltage Input. Connect AVIN directly to the input supply line.
Analog Signal Ground
Undervoltage Lockout Input. An external voltage-divider from the input supply sets the startup voltage;
the threshold is 1.24V with 130mV hysteresis. UVLO can also be used as a shutdown input. If unused,
connect UVLO to REG5
Startup Input. STARTUP coordinates simultaneous startup of multiple units from faults, during initial turn-
on, and UVLO recovery. When paralleling the secondaries of two MAX5051 ’ s, the STARTUP inputs of
each device must be connected together.
Fault Integration Input. During persistent current-limit faults, a capacitor connected to FLTINT is charged
with an internal 90μA current source. Switching is terminated when the voltage reaches 2.9V. An external
resistor connected in parallel discharges the capacitor. Switching resumes when the voltage drops to 2V.
Synchronization Input. SYNCIN accepts the synchronization signal from SYNCOUT of another MAX5051
and shifts the switching of the synchronized unit by 180 ° allowing the reduction of input bypass
capacitors. The MAX5051 switches at the same frequency at SYNCIN. SYNCIN must be 50% duty cycle.
Leave SYNCIN floating if unused.
10
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