参数资料
型号: MAX5066AUI+T
厂商: Maxim Integrated Products
文件页数: 11/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 2
频率 - 最大: 1MHz
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Finally, a thermal-shutdown feature protects the device
during thermal faults and shuts down the MAX5066
when the die temperature exceeds +160°C.
Dual-Output/Dual-Phase Select (MODE)
The MAX5066 can operate as a dual-output indepen-
dently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1 ) and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic high), VEA2 is dis-
connected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
Supply Voltage Connections (V IN /V REG )
The MAX5066 accepts a wide input voltage range at IN
of 5V to 28V. An internal linear regulator steps down V IN
to 5.1V (typ) and provides power to the MAX5066. The
output of this regulator is available at REG. For V IN =
4.75V to 5.5V, connect IN and REG together externally.
REG can supply up to 65mA for external loads. Bypass
REG to AGND with a 4.7μF ceramic capacitor for high-
frequency noise rejection and stable operation.
REG supplies the current for both the MAX5066’s inter-
nal circuitry and for the MOSFET gate drivers (when
connected externally to V DD ), and can source up to
65mA. Calculate the maximum bias current (I BIAS ) for
the MAX5066:
I BIAS = I IN + f SW × ( Q GQ 1 + Q GQ 2 + Q GQ 3 + Q GQ 4 )
where I IN is the quiescent supply current into IN (4mA,
typ), Q GQ1 , Q GQ2 , Q GQ3 , Q GQ4 are the total gate
charges of MOSFETs Q1 through Q4 at V GS = 5V (see
Figure 6 ), and f SW is the switching frequency of each
individual phase.
diodes D1 and D2 (see Figure 6). Connect a 0.1μF
ceramic capacitor between BST_ and LX_.
Minimize the trace inductance from BST_ and V DD to
rectifier diodes, D1 and D2, and from BST_ and LX_ to
the boost capacitors, C8 and C9 (see Figure 6). This is
accomplished by using short, wide trace lengths.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX5066 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold monitors V REG and is inter-
nally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates “chattering” during
startup. Most of the internal circuitry, including the
oscillator, turns on when V REG reaches 4.5V. The
MAX5066 draws up to 4mA (typ) of current before
V REG reaches the UVLO threshold.
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6) . The voltage at the current-
error amplifier output limits the maximum current avail-
able to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Setting the Switching Frequency (f SW )
An internal oscillator generates the 180 o out-of-phase
clock signals required for both PWM modulators. The
oscillator also generates the 2V P-P voltage ramps nec-
essary for the PWM comparators. The oscillator fre-
quency can be set from 200kHz to 2MHz by an external
resistor (R T ) connected from RT/CLKIN to AGND (see
Figure 6). The equation below shows the relationship
between R T and the switching frequency:
Low-Side MOSFET Driver Supply (V DD )
V DD is the power input for the low-side MOSFET dri-
vers. Connect the regulator output REG externally to
f OSC =
2 . 5 × 10 10
R RT
Hz
V DD through an R-C lowpass filter. Use a 1 ? resistor
and a parallel combination of 1μF and 0.1μF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
Connect BST1 and BST2 to V DD through rectifier
where R RT is in ohms and f SW(PER PHASE) = f OSC /2.
Use RT/CLKIN as a clock input to synchronize the
MAX5066 to an external frequency (f RT/CLKIN ). Applying
an external clock to RT/CLKIN allows each PWM section
to work at a frequency equal to f RT/CLKIN /2. An internal
comparator with a 1.6V threshold detects f RT/CLKIN . If
f RT/CLKIN is present, internal logic switches from the
internal oscillator clock, to the clock present at
RT/CLKIN.
______________________________________________________________________________________
11
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MAX5066EUI+T 功能描述:DC/DC 开关控制器 Synch Buck Controller RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK
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