参数资料
型号: MAX5066EUI+
厂商: Maxim Integrated Products
文件页数: 18/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 2
频率 - 最大: 1MHz
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
Losses associated with MOSFET on-time and
SEGMENT LOSS
P CONDUCTION = I RMS 2 × R DS ( ON )
Conduction Loss
on-resistance. I RMS is a function of load current
and duty cycle.
where I RMS ≈
V OUT
V IN
× I LOAD
Losses associated with charging and
Gate Drive Loss
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q G )
specification.
Losses during the drain voltage and drain
P GATEDRIVE = V DD × Q G × f SW
current transitions for every switching cycle.
Losses occur only during the Q GS2 and Q GD
time period and not during the initial Q GS1
P SWITCH = V IN × I LOAD × f SW ×
(Q GS2 + Q GD )
I GATE
Switching Loss
period. The initial Q GS1 period is the rise in the
gate voltage from zero to V TH.
R DH is the high-side MOSFET driver’s on-
resistance and R GATE is the internal gate
where I GATE =
V DD
2 × ( R DH + R GATE )
resistance of the high-side MOSFET (Q GD and
Q GS2 are found in the MOSFET data sheet).
Losses associated with Q OSS of the MOSFET
Output Loss
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs but are dissipated in the high-side
P OUTPUT =
Q OSS ( HS ) + Q OSS ( LS )
2
× V IN × f SW
MOSFET.
worst-case RMS current occurs when only one con-
troller section is operating. The controller section with
the highest output power needs to be used in determin-
ing the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other out-
of-phase controller section results in reducing the input
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R ESR_OUT ).
The peak-to-peak inductor current ripple is given by:
? I L = OUT
I CIN ( RMS ) ≈ I MAX
V OUT ( V IN ? V OUT )
V IN
V   (1 ? D)
L × f SW
During a load step, the allowable deviation of the out-
where I MAX is the full load current of the regulator.
V OUT is the output voltage of the same regulator and
C IN is C5 in Figure 6. The ESR of the input capacitors
wastes power from the input and heats up the capaci-
tor. Reducing the ESR is important to maintain a high
overall efficiency and in reducing the heating of the
capacitors.
put voltage during the fast transient load dictates the
output capacitance and ESR. The output capacitors
supply the load step until the controller responds with a
greater duty cycle. The response time (t RESPONSE )
depends on the closed-loop bandwidth of the regula-
tor. The resistive drop across the capacitor’s ESR and
capacitor discharge causes a voltage drop during a
18
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