参数资料
型号: MAX5066EUI+
厂商: Maxim Integrated Products
文件页数: 8/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 2
频率 - 最大: 1MHz
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
NAME
CSN2
CSP2
EAOUT2
EAN2
CLP2
REF
RT/CLKIN
AGND
MODE
CLP1
EAN1
EAOUT1
CSP1
FUNCTION
Current-Sense Differential Amplifier Negative Input for Output2. Connect CSN2 to the negative
terminal of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified
by the current-sense amplifier (A V(CS) = 36V/V).
Current-Sense Differential Amplifier Positive Input for Output2. Connect CSP2 to the positive terminal
of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the
current-sense amplifier (A V(CS) = 36V/V).
Voltage Error-Amplifier Output2. Connect to an external gain-setting feedback resistor. The error-
amplifier gain determines the output voltage load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT2 to EAN2. A resistive
network results in a drooped output voltage regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
Voltage Error-Amplifier Inverting Input for Output2. Connect a resistive divider from V OUT2 to EAN2 to
AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A
resistive network results in a drooped output-voltage-regulation characteristic. An integrator
configuration results in very tight output-voltage regulation (see the Adaptive Voltage Positioning
section).
Current-Error Amplifier Output2. Compensate the current loop by connecting an R-C network from
CLP2 to AGND.
3.3V Reference Output. Bypass REF to AGND with a minimum 0.1μF ceramic capacitor. REF can
source up to 200μA for external loads.
External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to
AGND to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency
synchronization.
Analog Ground
Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck
regulator. When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see
Figure 1) and the device operates as a two-output, out-of-phase buck regulator. When MODE is
connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.
Current-Error Amplifier Output1. Compensate the current loop by connecting an R-C network from
CLP1 to AGND.
Voltage Error Amplifier Inverting Input for Output1. Connect a resistive divider from V OUT1 to EAN1 to
regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
Voltage Error Amplifier Output1. Connect to an external gain-setting feedback resistor. The error
amplifier gain determines the output-voltage-load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output-voltage regulation (see the Adaptive Voltage Positioning section).
Current-Sense Differential Amplifier Positive Input for Output1. Connect CSP1 to the positive terminal
of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the
current-sense amplifier (A V(CS) = 36V/V).
8
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