参数资料
型号: MAX5069DAUE+
厂商: Maxim Integrated Products
文件页数: 8/19页
文件大小: 0K
描述: IC REG CTRLR ISO PWM CM 16-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
PWM 型: 电流模式
输出数: 2
频率 - 最大: 2.5MHz
占空比: 100%
电源电压: 10.8 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
High-Frequency, Current-Mode PWM Controller
with Accurate Oscillator and Dual FET Drivers
Pin Description
PIN
MAX5069A
MAX5069D
1
2
3
4
5
6
7
MAX5069B
MAX5069C
1
2
3
4
5
6
7
NAME
RT
SYNC
HYST
SCOMP
DT
UVLO/EN
FB
COMP
FUNCTION
Oscillator-Timing Resistor. Connect a resistor from RT to AGND to set the internal oscillator
frequency.
External-Clock Sync Input. Connect SYNC to AGND when not using an external clock.
Hysteresis Input
Slope-Compensation Capacitor Connection
Dead-Time Resistor Connection. Connect a resistor from DT to AGND to program the
output dead time. Connect to REG5 for NDRVA and NDRVB maximum 50% duty cycle.
Externally Programmable Undervoltage Lockout. UVLO/EN programs the input start
voltage. Connect UVLO/EN to AGND to disable the output.
Error-Amplifier Inverting Input
Error-Amplifier Output
Fault-Integration Input. A capacitor connected to FLTINT charges with an internal 60μA
8
8
FLTINT
current source during persistent current-limit faults. Switching terminates when V FLTINT is
2.8V. An external resistor connected in parallel discharges the capacitor. Switching
resumes when V FLTINT drops to 1.6V.
9
10
11
12
13
14
15
16
EP
9
10
11
12
13
14
15
16
EP
CS
AGND
PGND
NDRVB
NDRVA
V CC
IN
REG5
PAD
Current-Sense Resistor Connection
Analog Ground. Connect to PGND.
Power Ground. Connect to AGND through a ground plane.
Gate-Driver Output B. Connect NDRVB to the gate of the external N-channel FET.
Gate-Driver Output A. Connect NDRVA to the gate of the external N-channel FET.
9V Linear-Regulator Output. Decouple V CC with a minimum 1μF ceramic capacitor to
AGND; also internally connected to the FET drivers.
Power-Supply Input. IN provides power for all internal circuitry except the gate driver.
Decouple IN with 0.1μF to AGND (see the Typical Operating Circuit ).
5V Linear-Regulator Output. Decouple REG5 to AGND with 0.1μF ceramic capacitor.
Exposed Paddle. Connect to GND.
8
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